LT3752 datasheet(40/52 Pages) AD

40 / 52 page

LT3752/LT3752-1

Rev. C

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RPRI = primary winding resistance

RSEC = secondary winding resistance

If there is a large difference between the core losses and

the copper losses then the number of secondary turns

can be adjusted to achieve a more suitable balance. The

number of primary turns should then be recalculated to

maintain the desired turns ratio.

Primary-Side Power MOSFET Selection

Theselectionoftheprimary-sideN-channelpowerMOSFET

M1 is determined by the maximum levels expected for the

drain voltage and drain current. In addition, the power

losses due to conduction losses, gate driver losses and

transition losses will lead to a fine tuning of the MOSFET

selection. If power losses are high enough to cause an

unacceptabletemperatureriseintheMOSFETthenseveral

MOSFETs may be required to be connected in parallel.

The maximum drain voltage expected for the MOSFET M1

follows from the equations previously stated in the active

clamp topology sections:

VDS (M1) = VIN2/(VIN – (VOUT • N))

The MOSFET should be selected with a BVDSS rating ap-

proximately 20% greater than the above steady state VDS

calculation due to tolerances in duty cycle, load transients,

voltage ripple on CCL and leakage inductance spikes. A

MOSFET with the lowest possible voltage rating for the

application should be selected to minimize switch on re-

sistance for improved efficiency. In addition, the MOSFET

should be selected with the lowest gate charge to further

minimize losses.

MOSFET M1 losses at maximum output current can be

approximated as :

PM1 = PCONDUCTION + PGATEDRIVER + PTRANSITION

(i) PCONDUCTION = (NP/NS) • (VOUT/VIN) • (NS/NP •

IOUT(MAX))2 • RDS(ON)

Note: The on resistance of the MOSFET, RDS(ON), in-

creases with the MOSFET’s junction temperature. RDS(ON)

should therefore be recalculated once junction tem-

perature is known. A final value for RDS(ON) and therefore

PCONDUCTION can be achieved from a few iterations.

(ii) PGATEDRIVER = (QG • INTVCC • fOSC)

where,

QG = gate charge (VGS = INTVCC)

(iii) PTRANSITION = PTURN_OFF + PTURN_ON (≈ 0 if ZVS)

(a) PTURN_OFF = (1/2)IOUT(MAX)(NS/NP)(VIN/1-D)

(QGD/IGATE) • fOSC

where,

QGD = gate to drain charge

IGATE = 2A source/sink for OUT pin gate driver

(b)PTURN_ON=(1/2)IOUT(MAX)(NS/NP)(VDS)(QGD/IGATE)

• fOSC

where,

VDS = M1 drain voltage at the beginning of M1 turn on

VDS typically sits between VIN and 0V (ZVS)

DuringprogrammabletimingtAO,negativeIMAGdischarges

M1 drain SWP towards VIN (Figure 1). ZVS is achieved if

enough leakage inductance exists—to delay the second-

ary side from clamping M1 drain to VIN—and if enough

energy is stored in LMAG to discharge SWP to 0V during

thatdelay.(seeProgrammingActiveClampSwitchTiming:

AOUT to OUT (tAO)).

Synchronous Control (SOUT)

The LT3752 / LT3752-1 use the SOUT pin to communicate

synchronous control information to the secondary side

synchronous rectifier controller (Figure 19). The isolating

transformer(TSYNC),couplingcapacitor(CSYNC)andresis-

tive load (RSYNC)allowthegroundreferencedSOUTsignal

to generate positive and negative signals required at the

SYNC input of the secondary side synchronous rectifier

controller. For the typical LT3752/LT3752-1 applications

operating with an LT8311, CSYNC is 220pF, RSYNC is 560Ω

and TSYNC is typically a PULSE PE-68386NL.

APPLICATIONS INFORMATION

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