LT3752 datasheet(42/52 Pages) AD

42 / 52 page

LT3752/LT3752-1

Rev. C

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A small 1µF bypass capacitor should also be placed close

to the IC between VIN and GND.

Asinputvoltagelevelsincrease,anyuseofbulkcapacitance

to minimize input ripple can impact on solution size and

cost. In addition, inputs with higher source impedance will

cause an increase in voltage ripple. In these applications it

is recommended to include an LC input filter. The output

impedance of the input filter should remain below the

negative input impedance of the DC/DC forward converter.

PCB Layout / Thermal Guidelines

For proper operation, PCB layout must be given special

attention. Critical programming signals must be able to

co-exist with high dv/dt signals. Compact layout can be

achieved but not at the cost of poor thermal management.

The following guidelines should be followed to approach

optimal performance.

1. Ensure that a local bypass capacitor is used (and placed

as close as possible) between VIN and GND for the

controller IC(s).

2. The critical programming resistors for timing (pins

TAO,TAS,TOS,TBLNK,IVSECandRT)mustuseshorttraces

to each pin. Each resistor should also use a short trace

toconnecttoasinglegroundbusspecificallyconnected

to pin 18 of the IC (GND).

3.Thecurrentsenseresistorfortheforwardconvertermust

use short Kelvin connections to the ISENSEPandISENSEN

pins. The current sense resistor for the housekeeping

supply should have it’s ground connection as close as

possible to the power ground (PGND) pin 38.

4. High dv/dt lines should be kept away from all timing

resistors, current sense inputs, HCOMP/COMP pins,

UVLO_VSEC/OVLO pins and both HFB and FB feedback

traces.

5. Gate driver traces (HOUT, AOUT, SOUT, OUT) should be

kept as short as possible.

6. When working with high power components, multiple

parallel components are the best method for spread-

ing out power dissipation and minimizing temperature

rise. In particular, multiple copper layers connected

by vias should be used to sink heat away from each

power MOSFET.

7. Keep high switching current PGND paths away from

signal ground. Also minimize trace lengths for those

high current switching paths to minimize parasitic

inductance.

APPLICATIONS INFORMATION

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