LT3752 datasheet(13/52 Pages) AD

13 / 52 page

LT3752/LT3752-1

Rev. C

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TYPICAL PERFORMANCE CHARACTERISTICS T

A = 25°C, unless otherwise noted.

Required RIVSEC vs Switching

Frequency (for DVSEC × 100 = 72.5%,

UVLO_VSEC = 1.25V)

OUT Pin Rise/Fall Times

vs OUT Pin Load Capacitance

OUT Maximum Duty Cycle Clamp

(DVSEC) vs UVLO_VSEC

SWITCHING FREQUENCY (kHz)

100

160

140

120

100

250

450

400

3752 G34

500

200

150

300 350

OUT PIN LOAD CAPACITANCE (nF)

3752 G35

INTVCC = 12V

(OVERDRIVEN FROM

HOUSEKEEPING SUPPLY)

UVLO_VSEC (V)

3.75

8.75

7.5

3752 G33

2.5

1.25

6.25

VIN = 12V

RT = 24.9k (300kHz)

RIVSEC = 51.1k

PIN FUNCTIONS

HFB (Pin 1): Housekeeping Supply Error Amplifier

Inverting Input.

HCOMP (Pin 2): Housekeeping Supply Error Amplifier

Output and Compensation Pin.

RT (Pin 3): A resistor to ground programs switching

frequency.

FB (Pin 4): Error Amplifier Inverting Input.

COMP (Pin 5): Error Amplifier Output. Allows various

compensation networks for nonisolated applications.

SYNC(Pin6):Allowssynchronizationofinternaloscillator

to an external clock. fSYNC equal to fOSC allowed.

SS1 (Pin 7): Capacitor controls soft-start/stop of switch-

ing frequency and volt-second clamp. During soft-stop it

also controls the COMP pin.

IVSEC (Pin 8): Resistor Programs OUT Pin Maximum

Duty Cycle Clamp (DVSEC). This clamp moves inversely

proportional to system input voltage to provide a volt-

second clamp.

UVLO_VSEC (Pin 9): A resistor divider from system in-

put allows switch maximum duty cycle to vary inversely

proportional with system input. This volt-second clamp

prevents transformer saturation for duty cycles above

50%.Resistordividerratioprogramsundervoltagelockout

(UVLO) threshold. A 5µA pin current hysteresis allows

programmingofUVLOhysteresis.Pinbelow0.4Vreduces

VIN currents to microamps.

OVLO (Pin 10): A resistor divider from system input

programs overvoltage lockout (OVLO) threshold. Fixed

hysteresis included.

TAO (Pin 11): A resistor programs nonoverlap timing

between AOUT rise and OUT rise control signals.

TAS(Pin12):ResistorsatTAOandTASdefinedelaybetween

SOUT fall and OUT rise (= tAO – tAS).

TOS (Pin 13): Resistor programs delay between OUT fall

and SOUT rise.

TBLNK (Pin 14): Resistor programs extended blanking of

ISENSEP and OC signals during MOSFET turn-on.

NC (Pins 15, 16, 37): No Connect Pins. These pins are not

connected inside the IC. These pins should be left open.

SS2 (Pin 17): Capacitor controls soft-start of COMP pin.

Alternatively can connect to OPTO to communicate start of

switching to secondary side. If unused, leave the pin open.

GND(Pin18):AnalogSignalGround.Electricalconnection

exists inside the IC to the exposed pad (Pin 39).

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