LT3752 datasheet(35/52 Pages) AD

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LT3752/LT3752-1

Rev. C

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APPLICATIONS INFORMATION

Programming Active Clamp Switch Timing: AOUT to

OUT (tAO) and OUT to AOUT (tOA) Delays

ThetimingstAOandtOArepresentthedelaysbetweenAOUT

and OUT edges (Figures 1 and 2) and are programmed

by a single resistor, RTAO, connected from analog ground

(Pin 18) to the TAO pin. Once tAO is programmed for the

reasons given below, tOA will be automatically generated.

Front-end timing tAO (M2 off, M1 on)

= AOUT(edge)-to-OUT(rising)

= 50ns + 3.8ns •

RTAO







 , 14.7k < RTAO < 125k

In order to minimize turn-on transition loss in M1 the drain

of M1 should be as low as possible before M1 turns on.

To achieve this, AOUT should turn M2 off a delay of tAO

beforeOUTturnsM1on.Thisallowsthemaintransformer’s

magnetizing current to discharge M1 drain voltage quickly

towards VIN before M1 turns on.

As SWP falls below VIN, however, the rectifying diodes on

the secondary side are typically active and clamp the SWP

node close to VIN. If enough leakage inductance exists,

however, the clamping action on SWP by the secondary

side will be delayed—potentially allowing the drain of

M1 to be fully discharged to ground just before M1 turns

on. Even with this delay due to the leakage inductance,

LMAG needs to be low enough to allow IMAG to be negative

enough to slew SWP down to ground before M1 turns on.

If achievable, M1 will experience zero voltage switching

(ZVS) for highest efficiency. As will be seen in a later sec-

tion entitled Primary-Side Power MOSFET Selection, M1

transition loss is a significant contributor to M1 losses.

Back-end timing tOA (M1 off, M2 on) is automatically

generated

= OUT(falling)-to-AOUT(edge) = 0.9 • tAO

tOA should be checked to ensure M2 is not turned on until

M1 and M3 are turned off.

Programming Synchronous Rectifier Timing: SOUT to

OUT (tSO) and OUT to SOUT (tOS) Delays

The LT3752/LT3752-1 include a ±0.4A gate driver at the

SOUT pin to send a control signal via a pulse transformer

to the secondary side of the forward converter for syn-

chronous rectification (see Figures 1 and 2). For the

highest efficiency, M4 should be turned on whenever M1

is turned off. This suggests that SOUT should be a non-

overlapping signal with OUT with very small non-overlap

times. Inherent timing delays, however, which can vary

from application to application, can exist between OUT to

CSW and between SOUT to CG. Possible shoot-through

can occur if both M1 and M4 are on at the same time,

resulting in transformer and/or switch damage.

Front-end timing: tSO (M4 off, M1 on)

= SOUT(falling)-to-OUT(rising) delay

= tSO = tAO – tAS

= 3.8ns • (RTAS – RTAO)

where:

tAS = 50ns + (3.8ns • RTAS/1k) , 14.7k < RTAS < 125k,

tAO = 50ns + (3.8ns • RTAO/1k), 14.7k < RTAO < 125k,

tSO is defined by resistors RTAS and RTAO connected from

analog ground (Pin 18) to their respective pins TAS and

TAO. Each of these resistor defines a delay referenced

to the AOUT edge at the start of each cycle. RTAO was

already programmed based on requirements defined in

the previous section Programming AOUT to OUT Delay.

RTAS is then programmed as a delay from AOUT to SOUT

to fulfill the equation above for tSO. By choosing RTAS less

than or greater than RTAO, the delay between SOUT falling

and OUT rising can be programmed as positive or nega-

tive. While a positive delay can always be programmed

for tSO, the ability to program a negative delay allows for

improved efficiency if OUT(rising)-to-CSW(rising) delay

is larger than SOUT(falling)-to-CG(rising) delay.

LT3752 Datasheet(PDF) 35 Page - Analog Devices

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