LT3752 datasheet(30/52 Pages) AD

30 / 52 page

LT3752/LT3752-1

Rev. C

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APPLICATIONS INFORMATION

cally 0.75 but may be further limited by the transformer

design and voltage ratings of components connected to

the drain of the primary side power MOSFET (SWP). See

voltage calculations in the LO side and HI side active clamp

topologies sections.

If system input voltage falls below it's UVLO threshold

the part will enter soft-stop with continued switching.

The LT3752/LT3752-1 include an intelligent circuit which

prevents DVSEC from continuing to rise as system input

voltagefalls(seeSoft-Stop).Withoutthis,toolargeaDVSEC

would require extremely high reset voltages on the SWP

node to properly reset the transformer. The UVLO_VSEC

pin maximum operational level is the lesser of VIN – 2V

or 12.5V.

The LT3752/LT3752-1 volt-second clamp architecture

is superior to an external RC network connected from

system input to trip an internal comparator threshold.

The RC method suffers from external capacitor error, part-

to-part mismatch between the RC time constant and the

IC’s switching period, the error of the internal comparator

threshold and the nonlinearity of charging at low input

voltages. The LT3752/LT3752-1 use the RIVSEC resistor to

define the charge current for an internal timer capacitor to

set an OUT pin maximum on-time, tON(VSEC). The voltage

across RIVSEC follows UVLO_VSEC pin voltage (divided

down from system input voltage). Hence, RIVSEC current

varies linearly with input supply. The LT3752/LT3752-1

also trim out internal timing capacitor and comparator

thresholderrorstooptimizepart-to-partmatchingbetween

tON(VSEC) and T.

DVSEC Open Loop Control: No Opto-Coupler, Error

Amplifier or Reference

The accuracy of the programmable volt-second clamp

(DVSEC) safely controls VOUT if open loop conditions exist

suchasnoopto-coupler,erroramplifierorreferenceonthe

secondary side. DVSECcontrolstheoutputoftheconverter

by controlling duty cycle inversely proportional to system

input. If DVSEC duty cycle guardrail is programmed X%

above natural duty cycle, VOUT will only increase by X%

if a closed loop system breaks open. This volt-second

clamp is operational over a 10:1 system input voltage

range. See DVSEC versus UVLO_VSEC pin voltage in the

Typical Performance Characteristics section.

RIVSEC: Open Pin Detection Provides Safety

The LT3752/LT3752-1 provide an open-detection safety

feature for the RIVSEC pin. If the RIVSEC resistor goes

open circuit the part immediately stops switching. This

prevents the part from running without the volt-second

clamp in place.

Transformer Reset: Active Clamp Technique

The LT3752/LT3752-1 include a ±0.4A gate driver at the

AOUT pin to allow the use of an active clamp transformer

reset technique (Figures 13, 17). The active clamp method

improves efficiency and reduces voltage stress on the

main power switch, M1. By switching in the active clamp

capacitor only when needed, the capacitor does not lose

its charge during M1 on-time. By allowing the active clamp

capacitor, CCL, to store the average voltage required to

reset the transformer, the main power switch sees lower

drain voltage.

An imbalance of volt-seconds will cause magnetizing cur-

rent to walk upwards or downwards until the active clamp

capacitor is charged to the optimal voltage for proper

transformer reset. The voltage rating of the capacitor will

depend on whether the active clamp capacitor is actively

switched to ground (Figure 13) or actively switched to

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