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DS3172 Datasheet(PDF) 155 Page - Dallas Semiconductor

Part # DS3172
Description  Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers
PDF  232 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS3172 Datasheet(HTML) 155 Page - Dallas Semiconductor

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as a zero followed by a BPV, and the first HDB3 signature is defined as two zeros followed by a BPV. All
subsequent B3ZS/HDB3 signatures will be determined by the setting of this bit.
Bit 0: Receive Zero Suppression Decoding Disable (RZSD) – When 0, the B3ZS/HDB3 Decoder performs zero
suppression (B3ZS or HDB3) and AMI decoding. When 1, zero suppression (B3ZS or HDB3) decoding is disabled,
and only AMI decoding is performed.
Register Name:
LINE.RSR
Register Description:
Line Receive Status Register
Register Address:
(0.2.4.6)94h
Bit #
15
14
13
12
11
10
9
8
Name
--
--
--
--
--
--
--
--
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
EXZC
--
BPVC
LOS
Bit 3: Excessive Zero Count (EXZC) – When 0, the excessive zero count is zero. When 1, the excessive zero
count is one or more.
Bit 1: Bipolar Violation Count (BPVC) – When 0, the bipolar violation count is zero. When 1, the bipolar violation
count is one or more.
Bit 0: Loss Of Signal (LOS) – When 0, the receive line is not in a loss of signal (LOS) condition. When 1, the
receive line is in an LOS condition. See Section 10.10.6.
Note: When zero suppression (B3ZS or HDB3) decoding is disabled, the LOS condition is cleared, and cannot be
detected
Register Name:
LINE.RSRL
Register Description:
Line Receive Status Register Latched
Register Address:
(0.2.4.6)96h
Bit #
15
14
13
12
11
10
9
8
Name
--
--
--
--
--
--
--
--
Bit #
7
6
5
4
3
2
1
0
Name
--
--
ZSCDL
EXZL
EXZCL
BPVL
BPVCL
LOSL
Bit 5: Zero Suppression Code Detect Latched (ZSCDL) – This bit is set when a B3ZS or HDB3 signature is
detected.
Bit 4: Excessive Zero Latched (EXZL) – This bit is set when an excessive zero event is detected on the incoming
bipolar data stream.
Bit 3: Excessive Zero Count Latched (EXZCL) – This bit is set when the LINE.RSR.EXZC bit transitions from
zero to one.
Bit 2: Bipolar Violation Latched (BPVL) – This bit is set when a bipolar violation (or E3 LCV if enabled) is
detected on the incoming bipolar data stream.
Bit 1: Bipolar Violation Count Latched (BPVCL) – This bit is set when the LINE.RSR.BPVC bit transitions from
zero to one.
Bit 0: Loss of Signal Change Latched (LOSL) – This bit is set when the LINE.RSR.LOS bit changes state.



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