DS3172 datasheet(159/232 Pages) DALLAS

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DS3171/DS3172/DS3173/DS3174

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Bit 2: Transmit Data Inversion Enable (TDIE) – When 0, the outgoing data is directly output from packet

processing. When 1, the outgoing data is inverted before being output from packet processing.

Bit 1: Transmit FCS Processing Disable (TFPD) – This bit controls whether or not an FCS is calculated and

appended to the end of each packet. When 0, the calculated FCS bytes are appended to the end of the packet.

When 1, the packet is transmitted without an FCS.

Bit 0: Transmit FIFO Reset (TFRST) – When 0, the Transmit FIFO will resume normal operations, however, data

is discarded until a start of packet is received after RAM power-up is completed. When 1, the Transmit FIFO is

emptied, any transfer in progress is halted, the FIFO RAM is powered down, and all incoming data is discarded (all

TFDR register writes are ignored).

HDLC.TFDR

HDLC Transmit FIFO Data Register

(0,2,4,6)A2h

Bit #

Name

TFD7

TFD6

TFD5

TFD4

TFD3

TFD2

TFD1

TFD0

Default

Bit #

Name

TDPE

Default

Note: The FIFO data and status are loaded into the Transmit FIFO when the Transmit FIFO Data (TFD[7:0]) is

written (upper byte write). When read, the value of these bits is always zero.

Bits 15 to 8: Transmit FIFO Data (TFD[7:0]) – These eight bits are the packet data to be stored in the Transmit

FIFO. TFD[7] is the MSB, and TFD[0] is the LSB. If bit reordering is disabled, TFD[0] is the first bit transmitted, and

TFD[7] is the last bit transmitted. If bit reordering is enabled, TFD[7] is the first bit transmitted, and TFD[0] is the

last bit transmitted.

Bit 0: Transmit FIFO Data Packet End (TDPE) – When 0, the Transmit FIFO data is not a packet end. When 1,

the Transmit FIFO data is a packet end.

HDLC.TSR

HDLC Transmit Status Register

(0,2,4,6)A4h

Bit #

Name

TFFL5

TFFL4

TFFL3

TFFL2

TFFL1

TFFL0

Bit #

Name

TFF

TFE

THDA

Bits 13 to 8: Transmit FIFO Fill Level (TFFL[5:0]) – These six bits indicate the number of eight byte groups

available for storage (do not contain data) in the Transmit FIFO. E.g., a value of 21 (15h) indicates the FIFO has

168 (A8h) to 175 (AFh) bytes are available for storage.

Bit 2: Transmit FIFO Full (TFF) – When 0, the Transmit FIFO contains 255 or less bytes of data. When 1, the

Transmit FIFO is full.

Bit 1: Transmit FIFO Empty (TFE) – When 0, the Transmit FIFO contains at least one byte of data. When 1, the

Transmit FIFO is empty.

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