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Bit 3: Transmit Packet End Interrupt Enable (TPEIE) – This bit enables an interrupt if the TPEL bit is set and the

bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.

0 = interrupt disabled

1 = interrupt enabled

Bit 2: Transmit FIFO Full Interrupt Enable (TFFIE) – This bit enables an interrupt if the TFFL bit is set and the bit

in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.

0 = interrupt disabled

1 = interrupt enabled

Bit 1: Transmit FIFO Empty Interrupt Enable (TFEIE) – This bit enables an interrupt if the TFEL bit is set and the

bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.

0 = interrupt disabled

1 = interrupt enabled

Bit 0: Transmit HDLC Data Available Interrupt Enable (THDAIE) – This bit enables an interrupt if the THDAL bit

is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.

0 = interrupt disabled

1 = interrupt enabled

12.6.2 HDLC Receive Side Register Map

The receive side utilizes five registers.

Table 12-18. Receive Side HDLC Register Map

Address

(0,2,4,6)B0h HDLC.RCR

HDLC Receive Control Register

(0,2,4,6)B2h

Unused

(0,2,4,6)B4h HDLC.RSR

HDLC Receive Status Register

(0,2,4,6)B6h HDLC.RSRL

HDLC Receive Status Register Latched

(0,2,4,6)B8h HDLC.RSRIE HDLC Receive Status Register Interrupt Enable

(0,2,4,6)BAh

Unused

(0,2,4,6)BCh HDLC.RFDR

HDLC Receive FIFO Data Register

(0,2,4,6)BEh

Unused

12.6.2.1 Register Bit Descriptions

HDLC.RCR

HDLC Receive Control Register

(0,2,4,6)B0h

Bit #

Name

RDAL4

RDAL3

RDAL2

RDAL1

RDAL0

Default

Bit #

Name

RBRE

RDIE

RFPD

RFRST

Default

Bits 13 to 8: Receive HDLC Data Available Level (RDAL[4:0]) – These five bits indicate the minimum number of

eight byte groups that must be stored (contain data) in the Receive FIFO before HDLC data is considered to be

available (RHDA=1). For example, a value of 21 (15h) results in HDLC data being available when the Receive

FIFO contains 168 (A8h) bytes or more.

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