DS3172 datasheet(162/232 Pages) DALLAS

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Bit 3: Receive Bit Reordering Enable (RBRE) – When 0, bit reordering is disabled (The first bit received is in the

LSB of the Receive FIFO Data byte RFD[0]). When 1, bit reordering is enabled (The first bit received is in the MSB

of the Receive FIFO Data byte RFD[7]).

Bit 2: Receive Data Inversion Enable (RDIE) – When 0, the incoming data is directly passed on for packet

processing. When 1, the incoming data is inverted before being passed on for packet processing.

Bit 1: Receive FCS Processing Disable (RFPD) – When 0, FCS processing is performed (the packets have an

FCS appended). When 1, FCS processing is disabled (the packets do not have an FCS appended).

Bit 0: Receive FIFO Reset (RFRST) – When 0, the Receive FIFO will resume normal operations, however, data is

discarded until a start of packet is received after RAM power-up is completed. When 1, the Receive FIFO is

emptied, any transfer in progress is halted, the FIFO RAM is powered down, the RHDA bit is forced low, and all

incoming data is discarded.

HDLC.RSR

HDLC Receive Status Register

(0,2,4,6)B4h

Bit #

Name

Bit #

Name

RFF

RFE

RHDA

Bit 2: Receive FIFO Full (RFF) – When 0, the Receive FIFO contains 255 or less bytes of data. When 1, the

Receive FIFO is full.

Bit 1: Receive FIFO Empty (RFE) – When 0, the Receive FIFO contains at least one byte of data. When 1, the

Receive FIFO is empty.

Bit 0: Receive HDLC Data Available (RHDA) – When 0, the Receive FIFO contains less data than the Receive

HDLC data available level (RDAL[4:0]). When 1, the Receive FIFO contains the same or more data than the

Receive HDLC data available level.

HDLC.RSRL

HDLC Receive Status Register Latched

(0,2,4,6)B6h

Bit #

Name

Bit #

Name

RFOL

RPEL

RPSL

RFFL

RHDAL

Bit 7: Receive FIFO Overflow Latched (RFOL) – This bit is set when a Receive FIFO overflow condition occurs.

An overflow condition results in a loss of data.

Bit 4: Receive Packet End Latched (RPEL) – This bit is set when an end of packet is stored in the Receive FIFO.

Bit 3: Receive Packet Start Latched (RPSL) – This bit is set when a start of packet is stored in the Receive FIFO.

Bit 2: Receive FIFO Full Latched (RFFL) – This bit is set when the RFF bit transitions from 0 to 1.

Bit 0: Receive HDLC Data Available Latched (RHDAL) – This bit is set when the RHDA bit transitions from 0 to

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