DS3172 datasheet(165/232 Pages) DALLAS

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DS3171/DS3172/DS3173/DS3174

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12.7 FEAC Controller

12.7.1 FEAC Transmit Side Register Map

The transmit side utilizes five registers.

Table 12-19. FEAC Transmit Side Register Map

Address

(0,2,4,6)C0h FEAC.TCR

FEAC Transmit Control Register

(0,2,4,6)C2h FEAC.TFDR

FEAC Transmit Data Register

(0,2,4,6)C4h FEAC.TSR

FEAC Transmit Status Register

(0,2,4,6)C6h FEAC.TSRL

FEAC Transmit Status Register Latched

(0,2,4,6)C8h FEAC.TSRIE

FEAC Transmit Status Register Interrupt Enable

(0,2,4,6)CAh

Unused

(0,2,4,6)CCh

Unused

(0,2,4,6)CEh

Unused

12.7.1.1 Register Bit Descriptions

FEAC.TCR

FEAC Transmit Control Register

(0,2,4,6)C0h

Bit #

Name

Default

Bit #

Name

TFCL

TFS1

TFS0

Default

Bit 2: Transmit FEAC Codeword Load (TFCL) – A 0 to 1 transition on this bit loads the transmit FEAC processor

mode select bits (TFS[1:0]), and transmit FEAC codes (TFCA[5:0] and TFCB[5:0]). Note: Whenever a FEAC

codeword is loaded, any current FEAC codeword transmission in progress will be immediately halted, and the new

FEAC codeword transmission will be started based on the new values for TFS[1:0], TFCA[5:0], and TFCB[5:0]..

Bits 1 to 0: Transmit FEAC Codeword Select (TFS[1:0]) – These two bits control the transmit FEAC processor

mode. The TFCL bit loads the mode set by this bit.

00 = Idle (all ones)

01 = single code (send code TFCA ten times and send all ones)

10 = dual code (send code TFCA ten times, send code TFCB ten times, and send all ones)

11 = continuous code (send code TFCA continuously)

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