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DS3172 Datasheet(PDF) 167 Page - Dallas Semiconductor

Part # DS3172
Description  Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers
PDF  232 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS3172 Datasheet(HTML) 167 Page - Dallas Semiconductor

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Register Name:
FEAC.TSRIE
Register Description:
FEAC Transmit Status Register Interrupt Enable
Register Address:
(0,2,4,6)C8h
Bit #
15
14
13
12
11
10
9
8
Name
--
--
--
--
--
--
--
--
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
--
--
--
TFIIE
Default
0
0
0
0
0
0
0
0
Bit 0: Transmit FEAC Idle Interrupt Enable (TFIIE) – This bit enables an interrupt if the TFIL bit is set and the bit
in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
12.7.2 FEAC Receive Side Register Map
The receive side utilizes five registers.
Table 12-20. FEAC Receive Side Register Map
Address
Register
Register Description
(0,2,4,6)D0h FEAC.RCR
FEAC Receive Control Register
(0,2,4,6)D2h
--
Unused
(0,2,4,6)D4h FEAC.RSR
FEAC Receive Status Register
(0,2,4,6)D6h FEAC.RSRL FEAC Receive Status Register Latched
(0,2,4,6)D8h FEAC.RSRIE FEAC Receive Status Register Interrupt Enable
(0,2,4,6)DAh
--
Unused
(0,2,4,6)DCh FEAC.RFDR FEAC Receive FIFO Data Register
(0,2,4,6)DEh
--
Unused
12.7.2.1 Register Bit Descriptions
Register Name:
FEAC.RCR
Register Description:
FEAC Receive Control Register
Register Address:
(0,2,4,6)D0h
Bit #
15
14
13
12
11
10
9
8
Name
--
--
--
--
--
--
--
--
Default
0
0
0
0
1
0
0
0
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
--
--
--
RFR
Default
0
0
0
0
0
0
0
0
Bit 0: Receive FEAC Reset (RFR) –When 0, the Receive FEAC Processor and Receive FEAC FIFO will resume
normal operations. When 1, the Receive FEAC controller is reset. The FEAC FIFO is emptied, any transfer in
progress is halted, and all incoming data is discarded.



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