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DS3172 Datasheet(PDF) 169 Page - Dallas Semiconductor

Part # DS3172
Description  Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers
PDF  232 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS3172 Datasheet(HTML) 169 Page - Dallas Semiconductor

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Bit 1: Receive FEAC Codeword Detect Interrupt Enable (RFCDIE) – This bit enables an interrupt if the RFCDL
bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 0: Receive FEAC Idle Interrupt Enable (RFIIE) – This bit enables an interrupt if the RFIL bit is set and the bit
in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
Register Name:
FEAC.RFDR
Register Description:
FEAC Receive FIFO Data Register
Register Address:
(0,2,4,6)DCh
Bit #
15
14
13
12
11
10
9
8
Name
--
--
--
--
--
--
--
--
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Name
RFFI
--
RFF5
RFF4
RFF3
RFF2
RFF1
RFF0
Default
0
0
0
0
0
0
0
0
Bit 7: Receive FEAC FIFO Data Invalid (RFFI) – When 0, the Receive FIFO data (RFF[5:0]) is valid. When 1, the
Receive FIFO data is invalid (Receive FIFO is empty).
Bits 5 to 0: Receive FEAC FIFO Data (RFF[5:0]) – These six bits are the FEAC code data stored in the Receive
FIFO. RFF[5] is the LSB (last bit received) of the FEAC code (C[6]), and RFF[0] is the MSB (first bit received) of the
FEAC code (C[1]). The Receive FEAC FIFO data (RFF[5:0]) is updated when it is read (lower byte read).



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