DS3172 datasheet(170/232 Pages) DALLAS

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12.8 Trail Trace

12.8.1 Trail Trace Transmit Side

The transmit side utilizes three registers. Register Map

Table 12-21. Transmit Side Trail Trace Register Map

Address

(0,2,4,6)E8h TT.TCR

Trail Trace Transmit Control Register

(0,2,4,6)EAh TT.TTIAR

Trail Trace Transmit Identifier Address Register

(0,2,4,6)ECh TT.TIR

Trail Trace Transmit Identifier Register

(0,2,4,6)EEh

Unused

12.8.1.1 Register Bit Descriptions

TT.TCR

Trail Trace Transmit Control Register

(0,2,4,6)E8h

Bit #

Name

Default

Bit #

Name

Reserved

TMAD

TIDLE

TDIE

TBRE

Default

Bit 3: Transmit Multi-frame Alignment Insertion Disable (TMAD) – When 0, multi-frame alignment signal (MAS)

insertion is enabled, and the first bit transmitted of each trail trace byte is overwritten with an MAS bit. When 1,

MAS insertion is disabled, and the trail trace bytes from the Transmit Data Storage are output without being

modified.

Bit 2: Transmit Trail Trace Identifier Idle (TIDLE) – When 0, the programmed transmit trail trace identifier will be

transmitted. When 1, all zeros will be transmitted.

Bit 1: Transmit Data Inversion Enable (TDIE) – When 0, the outgoing data from trail trace processing is output

directly. When 1, the outgoing data from trail trace processing is inverted before being output.

Bit 0: Transmit Bit Reordering Enable (TBRE) – When 0, bit reordering is disabled (The first bit transmitted is the

MSB TT.TIR.TTD[7] of the byte). When 1, bit reordering is enabled (The first bit transmitted is the LSB

TT.TIR.TTD[0] of the byte).

DS3172 Datasheet(PDF) 170 Page - Dallas Semiconductor