VR4102 datasheet(20/701 Pages) NEC

20 / 701 page

LIST OF FIGURES (1/4)

Fig. No.

Title

Page

1-1

VR4102 Internal Block Diagram and Example of Connection to External Blocks...................................

1-2

VR4100 CPU Core Internal Block Diagram ............................................................................................43

1-3

VR4102 CPU Registers ..........................................................................................................................

1-4

CPU Instruction Formats........................................................................................................................

1-5

Little-Endian Byte Ordering in Word Data..............................................................................................

1-6

Little-Endian Byte Ordering in Double Word Data .................................................................................

1-7

Misaligned Word Accessing (Little-Endian) ...........................................................................................

1-8

CP0 Registers........................................................................................................................................

1-9

External Circuit of Clock Oscillator.........................................................................................................

1-10

Examples of Oscillator with Bad Connection .........................................................................................

2-1

VR4102 Signal Classification..................................................................................................................

3-1

CPU Instruction Formats........................................................................................................................

3-2

Byte Specification Related to Load and Store Instructions ....................................................................83

4-1

Pipeline Stages ......................................................................................................................................

4-2

Instruction Execution in the Pipeline ......................................................................................................

100

4-3

Pipeline Activities ...................................................................................................................................

100

4-4

Branch Delay .........................................................................................................................................

102

4-5

Add Instruction Pipeline Activities ..........................................................................................................

103

4-6

JALR Instruction Pipeline Activities .......................................................................................................

104

4-7

BEQ Instruction Pipeline Activities.........................................................................................................

105

4-8

TLT Instruction Pipeline Activities ..........................................................................................................

106

4-9

LW Instruction Pipeline Activities ...........................................................................................................

107

4-10

SW Instruction Pipeline Activities ..........................................................................................................

108

4-11

Interlocks, Exceptions, and Faults .........................................................................................................

109

4-12

Exception Detection ...............................................................................................................................

112

4-13

Data Cache Miss Stall............................................................................................................................

113

4-14

CACHE Instruction Stall.........................................................................................................................

113

4-15

Load Data Interlock................................................................................................................................

114

4-16

MD Busy Interlock..................................................................................................................................

114

5-1

Virtual-to-Physical Address Translation .................................................................................................

118

5-2

32-bit Mode Virtual Address Translation................................................................................................

119

5-3

64-bit Mode Virtual Address Translation................................................................................................

120

5-4

User Mode Address Space ....................................................................................................................

122

5-5

Supervisor Mode Address Space ..........................................................................................................

125

5-6

Kernel Mode Address Space .................................................................................................................

128

5-7

xkphys Area Address Space..................................................................................................................

129

5-8

VR4102 Physical Address Space ...........................................................................................................

135

5-9

CP0 Registers and the TLB ...................................................................................................................

141

5-10

Format of a TLB Entry............................................................................................................................

142

5-11

Format of a TLB Entry............................................................................................................................

143

VR4102 Datasheet(PDF) 20 Page - NEC

VR4102 Datasheet(HTML) 20 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL