VR4102 datasheet(52/701 Pages) NEC

52 / 701 page

CHAPTER 1 INTRODUCTION

1.6 CPU CORE MEMORY MANAGEMENT SYSTEM (MMU)

The VR4102 has a 32-bit physical addressing range of 4 Gbytes.

However, since it is rare for systems to

implement a physical memory space as large as that memory space, the CPU provides a logical expansion of

memory space by translating addresses composed in the large virtual address space into available physical memory

addresses. The VR4102 supports the following two addressing modes:

32-bit mode, in which the virtual address space is divided into 2 Gbytes for user process and 2 Gbytes for the

kernel.

64-bit mode, in which the virtual address is expanded to1 Tbyte (2

40 bytes) of user virtual address space.

A detailed description of these address spaces is given in Chapter 4.

1.6.1 Translation Lookaside Buffer (TLB)

The TLB converts virtual addresses to physical addresses. It runs by a full-associative method. It has 32 entries,

each mapping a pair of pages having a variable size (1 KB to 256 KB).

(1) Joint TLB (JTLB)

For fast virtual-to-physical address decoding, the VR4102 uses a large, fully associative TLB (joint TLB) that

translates 64 virtual pages to their corresponding physical addresses. The TLB is organized as 32 pairs of even-odd

entries, and maps a virtual address and address space identifier (ASID) into the 4-Gbyte physical address space.

The page size can be configured, on a per-entry basis, to map a page size of 1 KB to 256 KB. A CP0 register

stores the size of the page to be mapped, and that size is entered into the TLB when a new entry is written. Thus,

operating systems can provide special purpose maps; for example, a typical frame buffer can be memory-mapped

using only one TLB entry.

Translating a virtual address to a physical address begins by comparing the virtual address from the processor

with the physical addresses in the TLB; there is a match when the virtual page number (VPN) of the address is the

same as the VPN field of the entry, and either the Global (G) bit of the TLB entry is set, or the ASID field of the virtual

address is the same as the ASID field of the TLB entry.

This match is referred to as a TLB hit. If there is no match, a TLB Miss exception is taken by the processor and

software is allowed to refill the TLB from a page table of virtual/physical addresses in memory.

1.6.2 Operating Modes

The VR4102 has three operating modes:

— User mode

— Supervisor mode

— Kernel mode

The manner in which memory addresses are translated or mapped depends on these operating modes. Refer to

CHAPTER 5 MEMORY MANAGEMENT SYSTEM for details.

VR4102 Datasheet(PDF) 52 Page - NEC