VR4102 datasheet(63/701 Pages) NEC

63 / 701 page

CHAPTER 2 PIN FUNCTIONS

2.2.1 System Bus Interface Signals

These signals are used when the VR4102 is connected to a DRAM, ROM, or LCD, or other devices in the system

through the system bus.

Table 2-1. System Bus Interface Signals (1/2)

Signal

I/O

Description of function

ADD[25..0]

This is a 26-bit address bus. The VR4102 uses this to specify addresses for the DRAM, ROM, LCD, or

system bus (ISA).

DATA[15..0]

I/O

This is a 16-bit data bus. The VR4102 uses this to transmit and receive data with a DRAM, ROM, LCD,

or system bus.

DATA[31..16]/

GPIO[31..16]

I/O

This function differs depending on how the DBUS32 pin is set.

<When DBUS32 = 1> : DATA[31..16]

It is the high-order 16 bits of the 32-bit data bus.

This bus is used for transmitting and receiving data between the VR4102 and the DRAM and ROM.

<When DBUS32 = 0> : GPIO[31..16]

It is a general-purpose I/O (GPIO) port.

LCDCS#

This is the LCD chip select signal. This signal is active when the VR4102 is performing LCD access

using the ADD/DATA bus.

RD#

This is active when the VR4102 is reading data from the LCD, RAM, or ROM.

WR#

This is active when the VR4102 is writing data to the LCD, RAM, or ROM.

LCDRDY

This is the LCD ready signal. Set this signal as active when the LCD controller is ready to receive

access from the VR4102.

ROMCS[3..0]#

This is the ROM chip select signal. It is used to select a ROM to be accessed from among up to four

connected ROM units.

UUCAS#/

MRAS[3]#

This function differs depending on how the DBUS32 pin is set.

<When DBUS32 = 1> : UUCAS#

This signal is active when a valid column address is output via the ADD bus during access of

DATA[31:24] in the 32-bit data bus.

<When DBUS32 = 0> : MRAS[3]#

This is the DRAM’s RAS signal. Up to four DRAM units can be connected, and this signal is active

when a valid row address is output via the ADD bus for the DRAM connected to the high-order

address.

ULCAS#/

MRAS[2]#

This function differs depending on how the DBUS32 pin is set.

<When DBUS32 = 1> ULCAS#

This signal is active when a valid column address is output via the ADD bus during access of

DATA[23:16] in the 32-bit data bus.

<When DBUS32 = 0> MRAS[2]#

This is the DRAM’s RAS signal. This signal is active when a valid row address is output via the ADD

bus for the DRAM connected to the next-highest address after the highest high-order address.

MRAS[1..0]#

This is the DRAM’s RAS signal.

UCAS#

This is the DRAM’s CAS signal. This signal is active when a valid column address is output via the

ADD bus during access of DATA[15:8] in the DRAM.

LCAS#

This is the DRAM’s CAS signal. This signal is active when a valid column address is output via the

ADD bus during access of DATA[7:0] in the DRAM.

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