VR4102 datasheet(81/701 Pages) NEC

81 / 701 page

CHAPTER 3 CPU INSTRUCTION SET SUMMARY

This chapter is an overview of the central processing unit (CPU) instruction set; refer to the Chapter 27 for

detailed descriptions of individual CPU instructions.

3.1 CPU INSTRUCTION FORMATS

Each CPU instruction consists of a single 32-bit word, aligned on a word boundary. There are three instruction

formats - immediate (I-type), jump (J-type), and register (R-type) - as shown in Figure 3-1. The use of a small

number of instruction formats simplifies instruction decoding, allowing the compiler to synthesize more complicated

and less frequently used instruction and addressing modes from these three formats as needed.

Figure 3-1. CPU Instruction Formats

I-type (immediate)

J-type (jump)

target

R-type (register)

immediate:

func:

sa:

rd:

target:

6-bit function field

5-bit shift amount

5-bit destination register specifier

26-bit unconditional branch target address

16-bit immediate value, branch displacement or

address displacement

5-bit target (source/destination) register or branch

condition

6-bit operation code

5-bit source register specifier

rt:

rs:

op:

immediate

func

(1) Support of the MIPS ISA

The VR4102 does not support a multiprocessor operating environment.

Thus the synchronization support

instructions defined in the MIPS II and MIPS III ISA - the load linked and store conditional instructions - cause

reserved instruction exception. The load/link (LL) bit is eliminated.

Note that the SYNC instruction is handled as a NOP instruction since all load/store instructions in this processor

are executed in program order.

VR4102 Datasheet(PDF) 81 Page - NEC