VR4102 datasheet(23/701 Pages) NEC

23 / 701 page

LIST OF FIGURES (4/4)

Fig. No.

Title

Page

10-24

CBR Refresh (16-bit Mode) ....................................................................................................................

267

10-25

Self Refresh (16-bit Mode)......................................................................................................................

267

10-26

Bus Hold in Fullspeed Mode...................................................................................................................

268

10-27

Bus Hold in Suspend Mode ....................................................................................................................

269

11-1

DMA Space Used in DMA Transfers ......................................................................................................

271

13-1

Block Diagram of CMU and Peripheral Blocks .......................................................................................

289

14-1

Interrupt Control Outline .........................................................................................................................

293

15-1

Activation via Power Switch Interrupt (BATTINH/BATTINT# = 1)...........................................................

321

15-2

Activation via Power Switch Interrupt (BATTINH/BATTINT# = 0)...........................................................

321

15-3

Activation via GPIO Activation Interrupt (BATTINH/BATTINT# = 1) .......................................................

322

15-4

Activation via GPIO Activation Interrupt (BATTINH/BATTINT# = 0) .......................................................

322

15-5

Activation via DCD Interrupt (BATTINH/BATTINT# = 1).........................................................................

323

15-6

Activation via DCD Interrupt (BATTINH/BATTINT# = 0).........................................................................

323

15-7

Activation via Alarm Interrupt (BATTINH/BATTINT# = 1) .......................................................................

324

15-8

Activation via Alarm Interrupt (BATTINH/BATTINT# = 0) .......................................................................

324

15-9

Power Mode State Transition .................................................................................................................

325

19-1

PIU Peripheral Block Diagram ................................................................................................................

382

19-2

Equivalent Circuit of Coordinate Detection .............................................................................................

382

19-3

Internal Block Diagram of PIU ................................................................................................................

383

19-4

Scan Sequencer State Transition Diagram ............................................................................................

384

19-5

Interval Times and States .......................................................................................................................

391

19-6

Touch/Release Detection Timing............................................................................................................

404

19-7

A/D Port Scan Timing .............................................................................................................................

404

22-1

Data Format for Transmission and Reception ........................................................................................

448

22-2

Transmit Complete Interrupt Timing .......................................................................................................

450

22-3

Receive Complete Interrupt Timing ........................................................................................................

451

22-4

Receive Error Timing ..............................................................................................................................

452

24-1

Connection Example Between The VR4102 and IrDA Module ...............................................................

479

25-1

HSP Unit Block Diagram.........................................................................................................................

482

25-2

Circuit Configuration Block Diagram Examples ......................................................................................

482

25-3

Block Diagram of HSP Interface Power Control .....................................................................................

494

27-1

VR4102 Opcode Bit Encoding.................................................................................................................

674

29-1

Example of Connection of PLL Passive Components ............................................................................

683

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