VR4102 datasheet(50/701 Pages) NEC

50 / 701 page

CHAPTER 1 INTRODUCTION

Table 1-18. System Control Coprocessor (CP0) Register Definitions

Number

Description

Index

Programmable pointer to TLB array

Random

Pseudo-random pointer to TLB array (read only)

EntryLo0

Low half of TLB entry for even VPN

EntryLo1

Low half of TLB entry for odd VPN

Context

Pointer to kernel virtual PTE in 32-bit mode

PageMask

TLB page mask

Wired

Number of wired TLB entries



Reserved for future use

BadVAddr

Virtual address where the most recent error occurred

Count

Timer count

EntryHi

High half of TLB entry (including ASID)

Compare

Timer compare

Status

Status register

Cause

Cause of last exception

EPC

Exception Program Counter

PRId

Processor revision identifier

Config

Configuration register (specifying memory mode system)

LLAddr

Reserved

WatchLo

Memory reference trap address low bits

WatchHi

Memory reference trap address high bits

XContext

Pointer to kernel virtual PTE in 64-bit mode

21 to 25



Reserved for future use

PErr

Cache parity bits

CacheErr

Index and status of cache error

TagLo

Cache Tag register (low)

TagHi

Cache Tag register (high)

ErrorEPC

Error Exception Program Counter



Reserved for future use

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