VR4102 datasheet(10/701 Pages) NEC

10 / 701 page

CHAPTER 3 CPU INSTRUCTION SET SUMMARY ..........................................................................

3.1

CPU INSTRUCTION FORMATS ...........................................................................................

3.2

INSTRUCTION CLASSES......................................................................................................

3.2.1 Load and Store Instructions......................................................................................................

3.2.2 Computational Instructions.......................................................................................................

3.2.3 Jump and Branch Instructions..................................................................................................

3.2.4 Special Instructions ...................................................................................................................

3.2.5 System Control Coprocessor (CP0) Instructions ....................................................................

CHAPTER 4 VR4102 PIPELINE ...........................................................................................................

4.1

PIPELINE STAGES ................................................................................................................

4.1.1 Pipeline Activities....................................................................................................................... 100

4.2

BRANCH DELAY.................................................................................................................... 102

4.3

LOAD DELAY ......................................................................................................................... 102

4.4

PIPELINE OPERATION.......................................................................................................... 102

4.5

INTERLOCK AND EXCEPTION HANDLING....................................................................... 109

4.5.1 Exception Conditions................................................................................................................. 112

4.5.2 Stall Conditions .......................................................................................................................... 113

4.5.3 Slip Conditions ........................................................................................................................... 114

4.5.4 Bypassing ................................................................................................................................... 115

4.6

CODE COMPATIBILITY ......................................................................................................... 115

CHAPTER 5 MEMORY MANAGEMENT SYSTEM............................................................................. 117

5.1

TRANSLATION LOOKASIDE BUFFER (TLB) .................................................................... 117

5.2

VIRTUAL ADDRESS SPACE................................................................................................ 117

5.2.1 Virtual-to-Physical Address Translation .................................................................................. 118

5.2.2 32-bit Mode Address Translation.............................................................................................. 119

5.2.3 64-bit Mode Address Translation.............................................................................................. 120

5.2.4 Operating Modes ........................................................................................................................ 121

5.2.5 User Mode Virtual Addressing .................................................................................................. 121

5.2.6 Supervisor-mode Virtual Addressing ....................................................................................... 124

5.2.7 Kernel-mode Virtual Addressing............................................................................................... 127

5.3

PHYSICAL ADDRESS SPACE ............................................................................................. 135

5.3.1 ROM Space.................................................................................................................................. 137

5.3.2 System Bus Space ..................................................................................................................... 138

5.3.3 Internal I/O Space ....................................................................................................................... 139

5.3.4 LCD Space .................................................................................................................................. 140

5.3.5 DRAM Space ............................................................................................................................... 140

5.4

SYSTEM CONTROL COPROCESSOR ................................................................................ 141

5.4.1 Format of a TLB Entry................................................................................................................ 142

5.5

CP0 REGISTERS.................................................................................................................... 146

5.5.1 Index Register (0) ....................................................................................................................... 146

5.5.2 Random Register (1) .................................................................................................................. 146

5.5.3 EntryHi (10), EntryLo0 (2), EntryLo1 (3), and PageMask (5) Registers .................................. 147

5.5.4 Wired Register (6)....................................................................................................................... 148

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