VR4102 datasheet(9/701 Pages) NEC

9 / 701 page

CONTENTS

CHAPTER 1 INTRODUCTION ..............................................................................................................

1.1

FEATURES..............................................................................................................................

1.2

ORDERING INFORMATION ..................................................................................................

1.3

64-BIT ARCHITECTURE........................................................................................................

1.4

VR4102 PROCESSOR ............................................................................................................

1.4.1 Internal Block Structure.............................................................................................................

1.4.2 I/O Registers ...............................................................................................................................

1.5

VR4100 CPU CORE ...............................................................................................................

1.5.1 VR4100 CPU Core .......................................................................................................................

1.5.2 CPU Registers ............................................................................................................................

1.5.3 CPU Instruction Set Overview...................................................................................................

1.5.4 Data Formats and Addressing ..................................................................................................

1.5.5 Coprocessors (CP0-CP3)...........................................................................................................

1.5.6 Floating-Point Unit (FPU)...........................................................................................................

1.5.7 Cache ..........................................................................................................................................

1.6

CPU CORE MEMORY MANAGEMENT SYSTEM (MMU).................................................

1.6.1 Translation Lookaside Buffer (TLB) .........................................................................................

1.6.2 Operating Modes ........................................................................................................................

1.7

INSTRUCTION PIPELINE ......................................................................................................

1.8

CLOCK INTERFACE..............................................................................................................

CHAPTER 2 PIN FUNCTIONS.............................................................................................................

2.1

PIN CONFIGURATION...........................................................................................................57

2.2

PIN FUNCTION DESCRIPTION............................................................................................

2.2.1 System Bus Interface Signals ...................................................................................................

2.2.2 Clock Interface Signals..............................................................................................................

2.2.3 Battery Monitor Interface Signals .............................................................................................

2.2.4 Initialization Interface Signals...................................................................................................

2.2.5 RS-232-C Interface Signals........................................................................................................

2.2.6 IrDA Interface Signals ................................................................................................................

2.2.7 Debug Serial Interface Signals..................................................................................................

2.2.8 Keyboard Interface Signals .......................................................................................................

2.2.9 Audio Interface Signals .............................................................................................................

2.2.10 Touch Panel/General Purpose A/D Interface Signals ...........................................................

2.2.11 General-purpose I/O Signals ...................................................................................................

2.2.12 HSP MODEM Interface Signals ...............................................................................................

2.2.13 LED Interface Signal ................................................................................................................

2.2.14 Dedicated VDD and GND Signals .............................................................................................

2.3

PIN STATUS UPON SPECIFIC STATES ...........................................................................

2.3.1 Pin Status upon Reset ...............................................................................................................

2.3.2 Connection of Unused Pins and Pin I/O Circuits ....................................................................

2.3.3 Pin I/O Circuits ...........................................................................................................................

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