VR4102 datasheet(22/701 Pages) NEC

22 / 701 page

LIST OF FIGURES (3/4)

Fig. No.

Title

Page

8-7

Instruction Cache State Diagram ...........................................................................................................

219

8-8

Data flow on Instruction Fetch ...............................................................................................................

220

8-9

Data Integrity on Load Operations .........................................................................................................

221

8-10

Data Integrity on Store Operations ........................................................................................................

222

8-11

Data Integrity on Index_Invalidate Operations.......................................................................................

223

8-12

Data Integrity on Index_Writeback_Invalidate Operations.....................................................................

223

8-13

Data Integrity on Index_Load_Tag Operations ......................................................................................

224

8-14

Data Integrity on Index_Store_Tag Operations .....................................................................................

224

8-15

Data Integrity on Create_Dirty Operations.............................................................................................

225

8-16

Data Integrity on Hit_Invalidate Operations ...........................................................................................

225

8-17

Data Integrity on Hit_Writeback_Invalidate Operations .........................................................................

226

8-18

Data Integrity on Fill Operations ............................................................................................................

226

8-19

Data Integrity on Hit_Writeback Operations...........................................................................................

227

8-20

Data Integrity on Writeback Flow ...........................................................................................................

228

8-21

Data Integrity on Refill Flow ...................................................................................................................

228

8-22

Data Integrity on Writeback & Refill Flow...............................................................................................

229

9-1

Non-maskable Interrupt Signal ..............................................................................................................

231

9-2

Hardware Interrupt Signals ....................................................................................................................

233

9-3

Masking of the CPU Core Interrupts ......................................................................................................

234

10-1

ROM 4-byte Read, 16-bit Mode (WROMA[2:0] = 110)...........................................................................

253

10-2

ROM 4-byte Read, 32-bit Mode (WROMA[2:0] = 110)...........................................................................

253

10-3

PageROM 4-word Read, 16-bit Mode (WROMA[2:0] = 111, WPROM[1:0] = 10) ..................................

254

10-4

PageROM 4-word Read, 32-bit Mode (WROMA[2:0] = 111, WPROM[1:0] = 10) ..................................

255

10-5

Flash Memory Mode, 2-byte Access......................................................................................................

255

10-6

1-byte Access to Even Address Using 16-bit Bus (WISAA[2:0] = 101)..................................................

256

10-7

2-byte Access when Sampling IOCHRDY at High Level Using 16-bit Bus (WISAA[2:0] = 101) ............

257

10-8

1-byte Access to Odd Address Using 16-bit Bus (WISAA[2:0] = 101) ...................................................

258

10-9

1-byte Access to Odd Address Using 8-bit Bus (WISAA[2:0] = 101) .....................................................

258

10-10

2-byte Access when Sampling ZWS# at Low Level on 16-bit Bus (WISAA[2:0] = 101) ........................

259

10-11

2-byte Access when Sampling ZWS# at Low Level on 8-bit Bus (WISAA[2:0] = 101) ..........................

260

10-12

2-byte Access on 16-bit Bus (WLCD/M[2:0] = 101) ...............................................................................

261

10-13

1-byte Access on 8-bit Bus (WLCD/M[2:0] = 101) .................................................................................

261

10-14

2-byte Access When Sampling ZWS# at Low Level on 16-bit Bus (WLCD/M[2:0] = 101).....................

262

10-15

1-byte Access When Sampling ZWS# at Low Level on 8-bit Bus (WLCD/M[2:0] = 101).......................

262

10-16

2-byte Access to LCD Controller (WLCD/M[2:0] = 010).........................................................................

263

10-17

2-byte Access to LCD Controller (WLCD/M[2:0] = 011).........................................................................

263

10-18

4-byte Access to DRAM (16-bit Mode) ..................................................................................................

264

10-19

8-byte Access to DRAM (32-bit Mode) ..................................................................................................

264

10-20

Byte Read of Odd Address in DRAM (16-bit Mode)...............................................................................

265

10-21

Byte Read of Even Address in DRAM (16-bit Mode) .............................................................................

265

10-22

Byte Write to Odd Address in DRAM (16-bit Mode)...............................................................................

266

10-23

Byte Write to Even Address in DRAM (16-bit Mode) .............................................................................

266

VR4102 Datasheet(PDF) 22 Page - NEC

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