VR4102 datasheet(45/701 Pages) NEC

45 / 701 page

CHAPTER 1 INTRODUCTION

1.5.2 CPU Registers

The VR4100 CPU core has thirty two 64-bit general-purpose registers (GPRs).

In addition, the processor provides the following special, registers:

— 64-bit Program Counter (PC)

— 64-bit HI register, containing the integer multiply and divide upper doubleword result

— 64-bit LO register, containing the integer multiply and divide lower doubleword result

Two of the general-purpose registers have assigned the following functions:

— r0 is hardwired to a value of zero, and can be used as the target register for any instruction whose result is to

be discarded. r0 can also be used as a source when a zero value is needed.

— r31 is the link register used by link instruction, such as JAL/JALR instructions. This register can be used for

other instructions. However, be careful that use of the register by a link instruction will not coincide with use

of the register for other operations.

The register group is provided within the CP0, to process exceptions and to manage addresses.

CPU registers can operate as either 32-bit or 64-bit registers, depending on the VR4102 processor mode of

operation.

Figure 1-3 shows the CPU registers.

Figure 1-3. VR4102 CPU Registers

General-purpose register

r0 = 0

Multiply/divide register

Program Counter

r29

r30

r31 = LinkAddress

The VR4102 has no Program Status Word (PSW) register as such; this is covered by the Status and Cause

registers incorporated within the System Control Coprocessor (CP0).

The CP0 registers are used for exception handling or address management. The overview of these registers is

described in 1.5.5 Coprocessors (CP0-CP3).

VR4102 Datasheet(PDF) 45 Page - NEC