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SC3200 Datasheet(PDF) 201 Page - Advanced Micro Devices |
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SC3200 Datasheet(HTML) 201 Page - Advanced Micro Devices |
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201 / 447 page  AMD Geode™ SC3200 Processor Data Book 201 Core Logic Module - Register Summary Revision 5.1 Table 6-24. F5: PCI Header Registers for X-Bus Expansion Support Summary F5 Index Width (Bits) Type Name Reset Value Reference (Table 6-39) 00h-01h 16 RO Vendor Identification Register 100Bh Page 294 02h-03h 16 RO Device Identification Register 0505h Page 294 04h-05h 16 R/W PCI Command Register 0000h Page 294 06h-07h 16 RO PCI Status Register 0280h Page 294 08h 8 RO Device Revision ID Register 00h Page 294 09h-0Bh 24 RO PCI Class Code Register 068000h Page 294 0Ch 8 RO PCI Cache Line Size Register 00h Page 294 0Dh 8 RO PCI Latency Timer Register 00h Page 294 0Eh 8 RO PCI Header Type Register 00h Page 294 0Fh 8 RO PCI BIST Register 00h Page 294 10h-13h 32 R/W Base Address Register 0 (F5BAR0) — Sets the base address for the X-Bus Expansion support registers (summarized in Table 6-25.) 00000000h Page 294 14h-17h 32 R/W Base Address Register 1 (F5BAR1) — Reserved for possible future use by the Core Logic module. 00000000h Page 294 18h-1Bh 32 R/W Base Address Register 2 (F5BAR2) — Reserved for possible future use by the Core Logic module. 00000000h Page 294 1Ch-1Fh 32 R/W Base Address Register 3 (F5BAR3) — Reserved for possible future use by the Core Logic module. 00000000h Page 295 20h-23h 32 R/W Base Address Register 4 (F5BAR4) — Reserved for possible future use by the Core Logic module. 00000000h Page 295 24h-27h 32 R/W Base Address Register 5 (F5BAR5) — Reserved for possible future use by the Core Logic module. 00000000h Page 295 28h-2Bh --- --- Reserved 00h Page 295 2Ch-2Dh 16 RO Subsystem Vendor ID 100Bh Page 295 2Eh-2Fh 16 RO Subsystem ID 0505h Page 295 30h-3Fh --- --- Reserved 00h Page 295 40h-43h 32 R/W F5BAR0 Base Address Register Mask FFFFFFC1h Page 295 44h-47h 32 R/W F5BAR1 Base Address Register Mask 00000000h Page 296 48h-4Bh 32 R/W F5BAR2 Base Address Register Mask 00000000h Page 296 4Ch-4Fh 32 R/W F5BAR3 Base Address Register Mask 00000000h Page 296 50h-53h 32 R/W F5BAR4 Base Address Register Mask 00000000h Page 296 54h-57h 32 R/W F5BAR5 Base Address Register Mask 00000000h Page 296 58h 8 R/W F5BARx Initialized Register 00h Page 296 59h-FFh --- --- Reserved xxh Page 296 60h-63h 32 R/W Scratchpad for Chip Number 00000000h Page 296 64h-67h 32 R/W Scratchpad for Configuration Block Address 00000000h Page 297 68h-FFh --- --- Reserved 00h Page 297 Table 6-25. F5BAR0: I/O Control Support Registers Summary F5BAR0+ I/O Offset Width (Bits) Type Name Reset Value Reference (Table 6-40) 00h-03h 32 R/W I/O Control Register 1 010C0007h Page 298 04h-07h 32 R/W I/O Control Register 2 00000002h Page 299 08h-0Bh 32 R/W I/O Control Register 3 00009000h Page 299 |
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