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SC3200 Datasheet(PDF) 364 Page - Advanced Micro Devices

Part # SC3200
Description  AMD GEODE-TM SC3200 PROCESSOR
PDF  447 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

SC3200 Datasheet(HTML) 364 Page - Advanced Micro Devices

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364
AMD Geode™ SC3200 Processor Data Book
Video Processor Module - Video Processor Registers - Function 4
Revision 5.1
10
Auto-Flip. Video port operation mode.
0: The video port automatically detects the even and odd fields based on the VP_HREF and VP_VSYNC_IN signals or the
CCIR656 control codes.
1: The even/odd field detect logic is disabled and the video port automatically toggles between the even and odd buffers
during capture. The odd buffer is the first to be filled in this mode.
This bit must be programmed to 0 when Direct Video mode is used. Direct Video mode is used when VID_SEL = 10
(F4BAR0+Memory Offset 400h[1:0]). Otherwise the video select from the GX1 module. VID_SEL indicates the source of the
video data.)
9
Capture (Store to Memory) VBI Data.
0: Disable.
1: Enable.
8
Capture (Store to Memory) Video Data.
0: Disable.
1: Enable.
7:2
Reserved. Must be set to 0.
1:0
Run Mode Capture. Selects capture run mode.
00: Stop capture at end of current line.
01: Stop capture at end of current field.
10 Reserved.
11: Start capture at beginning of next field.
Offset 08h-0Bh
Video Interface Status Register (R/W)
Reset Value: xxxxxxxxh
31:25
Reserved. (Read Only)
24
Current Field. (Read Only)
0: Even field is being processed.
1: Odd field is being processed.
23:22
Reserved. (Read Only)
21
Base Register Not Updated. (Read Only) When set to 1, this bit indicates that one of the base registers (at
F4BAR2+Memory Offset 20h, 24h, 40h, and 44h) has been written but has not yet been updated.
0: All base registers are updated.
1: One or more of the base registers has not been updated.
20
FIFO Overflow Status Indication.
0: No overflow occurred.
1: An overflow occurred for the FIFO between the VIP and the Fast X-Bus.
Writing a 1 to this bit clears the status.
19:18
Reserved. (Read Only)
17
Line Interrupt (INTC#) Pending Status.
0: Interrupt not pending.
1: Interrupt pending.
Writing a 1 to this bit clears the status.
16
Field Interrupt (INTC) Pending Status.
0: Interrupt not pending.
1: Interrupt pending.
Writing a 1 to this bit clears the status.
15:10
Reserved. (Read Only)
9
VBI Data Capture Active. (Read Only)
0: VBI data is not being stored to memory.
1: VBI data is now being stored to memory.
Table 7-8. F4BAR2+Memory Offset: VIP Configuration Registers (Continued)
Bit
Description



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