SC3200 datasheet(370/447 Pages) AMD

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370

AMD Geode™ SC3200 Processor Data Book

Electrical Specifications

Revision 5.1

9.1.4

Operating Conditions

Table 9-3 lists the various power supplies of the SC3200 and provides the device operating conditions.

Notes:

All power sources except VBAT must be connected,

even if the function is not used.

VSB, and VSBL must be on if any other voltage is

applied. VSB and VBAT voltages can be applied sepa-

rately. See Section 9.3.15 "Power-Up Sequencing" on

page 434.

The power planes of the SC3200 can be turned on or

off. For more information, see Section 6.2.9 "Power

Management Logic" on page 174.

It is recommended that the voltage difference between

VCORE and VSBL be less than 0.25V, in order to reduce

leakage current. If the voltage difference exceeds

0.25V, excessive leakage current is used in gates that

are connected on the boundary between voltage

domains.

It is recommended that the voltage difference between

VIO and VSB be less than 0.25V, in order to reduce

leakage current. If the voltage difference exceeds

0.25V, excessive leakage current is used in gates that

are connected on the boundary between voltage

domains.

Table 9-3. Operating Conditions

Symbol

(Note 1)

Parameter

Min

Typ

Max

Unit

Comments

Operating case temperature

AVCCUSB

Analog power supply. Powers internal ana-

log circuits and some external signals (see

Table 9-4).

3.14

3.3

3.46

VBAT

Battery supply voltage. Powers RTC and

ACPI when VBAT is greater than VSB (by at

least 0.5V), and some external signals (see

Table 9-4).

2.4

3.0

3.46

VIO

I/O buffer power supply. Powers most of

the external signals (see Table 9-4); certain

signals within this power plane are 5V

tolerant.

3.14

3.3

3.46

VCORE

Core processor and internal digital power

supply. Powers internal digital logic, includ-

ing internal frequency multipliers.

1.71

1.8

1.89

VPLL2

VPLL3

PLL. Internal Phase Locked Loops (PLL)

power supply.

3.14

3.3

3.46

VSB

Standby power supply. Powers RTC and

ACPI when VSB is greater than VBAT-0.5V,

and some external signals (see Table 9-4).

3.14

3.3

3.46

VSBL

Standby logic. Powers internal logic

needed to support Standby VSB.

VSBL requires a 0.1 µF bypass capacitor to

VSS.

1.71

1.8

1.89

Note 1. For VIH (Input High Voltage), VIL (Input Low Voltage), IOH (Output High Current), and IOL (Output Low Current) op-

erating conditions refer to Section 9.2 "DC Characteristics" on page 375.

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