SC3200 datasheet(391/447 Pages) AMD

391 / 447 page

AMD Geode™ SC3200 Processor Data Book

391

Electrical Specifications

Revision 5.1

Figure 9-14. PCICLK Timing and Measurement Points

Table 9-18. PCI Clock Parameters

Symbol

Parameter

Min

Max

Unit

Comments

tCYC

PCICLK cycle time

Note 1

tHIGH

PCICLK high time

Note 2

tLOW

PCICLK low time

Note 2

PCICLKsr

PCICLK slew Rate

V/ns

Note 3

PCIRSTsr

PCIRST# slew Rate

mV/ns

Note 4

Note 1. Clock frequency is between nominal DC and 33 MHz. Device operational parameters at frequencies under 16 MHz

are not 100% tested. The clock can only be stopped in a low state.

Note 2. Guaranteed by characterization.

Note 3. Slew rate must be met across the minimum peak-to-peak portion of the clock waveform (see Figure 9-14).

Note 4. The minimum PCIRST# slew rate applies only to the rising (de-assertion) edge of the reset signal. See Figure 9-18

for PCIRST# timing.

tHIGH

0.4 VIO, p-to-p

(minimum)

0.6VIO

0.2VIO

0.5 VIO

0.4 VIO

0.3 VIO

tCYC

tLOW

PCICLK

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