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SC3200 Datasheet(PDF) 395 Page - Advanced Micro Devices |
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SC3200 Datasheet(HTML) 395 Page - Advanced Micro Devices |
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395 / 447 page ![]() AMD Geode™ SC3200 Processor Data Book 395 Electrical Specifications Revision 5.1 9.3.6 Sub-ISA Interface All output timing is guaranteed for 50 pF load, unless other- wise specified. The ISA Clock divisor (defined in F0 Index 50h[2:0] of the Core Logic module) is 011. Table 9-21. Sub-ISA Timing Parameters Symbol Parameter Bus Width (Bits) Type Min (ns) Max (ns) Figure Comments tRD1 MEMR#/DOCR#/RD#/TRDE# read active pulse width FE to RE 16 M 225 9-19 Standard tRD2 MEMR#/DOCR#/RD#/TRDE# read active pulse width FE to RE 16 M 105 9-19 Zero wait state tRD3 IOR#/RD#/TRDE# read active pulse width FE to RE 16 I/O 160 9-19 Standard tRD4 IOR#/MEMR#/DOCR#/RD#/TRDE# read active pulse width FE to RE 8 M, I/O 520 9-19 Standard tRD5 IOR#/MEMR#/DOCR#/RD#/TRDE# read active pulse width FE to RE 8 M, I/O 160 9-19 Zero wait state tRCU1 MEMR#/DOCR#/RD#/TRDE# inactive pulse width 16 M 103 9-19 tRCU2 MEMR#/DOCR#/RD#/TRDE# inactive pulse width 8M 163 9-19 tRCU3 IOR#/RD#/TRDE# inactive pulse width 8, 16 I/O 163 9-19 tWR1 MEMW#/WR# write active pulse width FE to RE 16 M 225 9-20 Standard tWR2 MEMW#/DOCW#/WR# write active pulse width FE to RE 16 M 105 9-20 Zero wait state tWR3 IOW#/WR# write active pulse width FE to RE 16 I/O 160 9-20 Standard tWR4 IOW#/MEMW#/DOCW#/WR# write active pulse width FE to RE 8 M, I/O 520 9-20 Standard tWR5 IOW#/MEMW#/DOCW#/WR# write active pulse width FE to RE 8 M, I/O 160 9-20 Zero wait state tWCU1 MEMW#/WR#/DOCW# inactive pulse width 16 M 103 9-20 tWCU2 MEMW#/WR#/DOCW# inactive pulse width 8M 163 9-20 tWCU3 IOW#/WR# inactive pulse width 8, 16 I/O 163 9-20 tRDYH IOR#/MEMR#/RD#/DOCR#/IOW#/ MEMW#/WR#/DOCW# hold after IOCHRDY RE 8, 16 M, I/O 120 9-19 9-20 tRDYA1 IOCHRDY valid after IOR#/MEMR#/ RD#/DOCR#/IOW#/MEMW#/WR#/ DOCW# FE 16 M, I/O 78 9-19 9-20 |
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