SC3200 datasheet(392/447 Pages) AMD

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392

AMD Geode™ SC3200 Processor Data Book

Electrical Specifications

Revision 5.1

Figure 9-15. Load Circuits for Maximum Time Measurements

Table 9-19. PCI Timing Parameters

Symbol

Parameter

Min

Max

Unit

Comments

tVAL

PCICLK to signal valid delay (on the bus)

Note 1, Note 2

tVAL(ptp)

PCICLK to signal valid delay (GNT#)

Note 1, Note 2

tON

Float to active delay

Note 1, Note 3,

tOFF

Active to float delay

Note 1, Note 3,

tSU

Input setup time to PCICLK (on the bus)

Note 4

tSU(ptp)

Input setup time to PCICLK (REQ#)

Note 4

Input hold time from PCICLK

Note 4

tRST

PCIRST# active time after power stable

Note 3, Note 5

tRST-CLK

PCIRST# active time after PCICLK stable

100

µs

Note 3, Note 5

tRST-OFF

PCIRST# active to output float delay

Note 3, Note 5,

Note 6

Note 1. See the timing measurement conditions in Figure 9-16.

Note 2. Minimum times are evaluated with same load used for slew rate measurement (as shown in note 3 of Table ); max-

imum times are evaluated with the load circuits shown in Figure 9-15, for high-going and low-going edges respec-

tively.

Note 3. Not 100% tested.

Note 4. See the timing measurement conditions in Figure 9-17.

Note 5. PCIRST# is asserted and de-asserted asynchronously with respect to PCICLK (see Figure 9-18).

Note 6. All output drivers are asynchronously floated when PCIRST# is active.

Output

Buffer

Output

Buffer

VCC

Ω

10 pF

0.5" max.

tVAL (Max) Rising Edge

tVAL (Max) Falling Edge

SC3200 Datasheet(PDF) 392 Page - Advanced Micro Devices

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