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SC3200 Datasheet(PDF) 403 Page - Advanced Micro Devices

Part # SC3200
Description  AMD GEODE-TM SC3200 PROCESSOR
PDF  447 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

SC3200 Datasheet(HTML) 403 Page - Advanced Micro Devices

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AMD Geode™ SC3200 Processor Data Book
403
Electrical Specifications
Revision 5.1
Table 9-25. IDE PIO Data Transfer to/from Device Timing Parameters
Symbol
Parameter
Mode
Unit
Comments
01234
t0
Cycle time (min)
600
383
240
180
120
ns
Note 1
t1
Address valid to IDE_IOR[0:1]#/
IDE_IOW[0:1]# setup (min)
70
50
30
30
25
ns
t2
IDE_IOR[0:1]#/IDE_IOW[0:1]# 16-bit
(min)
165
125
100
80
70
ns
Note 1
t2i
IDE_IOR[0:1]#/IDE_IOW[0:1]#
recovery time (min)
-
-
-
70
25
ns
Note 1
t3
IDE_IOW[0:1]# data setup (min)
6045303020
ns
t4
IDE_IOW[0:1]# data hold (min)
30
20
15
10
10
ns
t5
IDE_IOR[0:1]# data setup (min)
5035202020
ns
t6
IDE_IOR[0:1]# data hold (min)
55555
ns
t6Z
IDE_IOR[0:1]# data TRI-STATE
(max)
30
30
30
30
30
ns
Note 2
t9
IDE_IOR[0:1]#/IDE_IOW[0:1]# to
address valid hold (min)
20
15
10
10
10
ns
tRD
Read Data Valid to IDE_IORDY[0,1]
active (if IDE_IORDY[0:1] initially low
after tA) (min)
00000
ns
tA
IDE_IORDY[0:1] Setup time
35
35
35
35
35
ns
Note 3
tB
IDE_IORDY[0:1] Pulse Width (max)
1250
1250
1250
1250
1250
ns
tC
IDE_IORDY[0:1] assertion to release
(max)
55555
ns
Note 1. t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recov-
ery time or command inactive time. The actual cycle time equals the sum of the command active time and the com-
mand inactive time. The three timing requirements of t0, t2, and t2i are met. The minimum total cycle time
requirement is greater than the sum of t2 and t2i. (This means that a host implementation may lengthen t2 and/or
t2i to ensure that t0 is equal to or greater than the value reported in the device’s IDENTIFY DEVICE data.)
Note 2. This parameter specifies the time from the rising edge of IDE_IOR[0:1]# to the time that the data bus is no longer
driven by the device (TRI-STATE).
Note 3. The delay from the activation of IDE_IOR[0:1]# or IDE_IOW[0:1]# until the state of IDE_IORDY[0:1] is first sampled.
If IDE_IORDY[0:1] is inactive, then the host waits until IDE_IORDY[0:1] is active before the PIO cycle is completed.
If the device is not driving IDE_IORDY[0:1] negated after the activation (tA) of IDE_IOR[0:1]# or IDE_IOW[0:1]#,
then t5 is met and tRD is not applicable. If the device is driving IDE_IORDY[0:1] negated after the activation (tA) of
IDE_IOR[0:1]# or IDE_IOW[0:1]#, then tRD is met and t5 is not applicable.



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