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AMD Geode™ SC3200 Processor Data Book

Electrical Specifications

Revision 5.1

Figure 9-25. PIO Data Transfer to/from Device Timing Diagram

ADDR valid1

WRITE IDE_DATA[15:0]

READ IDE_DATA[15:0]

t2i

t6z

tRD

IDE_IOR0#

IDE_IOW0#

IDE_IORDY02,3

IDE_IORDY02,4

IDE_IORDY02,5

Notes:

Device address consists of signals IDE_CS[0:1]# and IDE_ADDR[2:0].

Negation of IDE_IORDY[0:1] is used to extend the PIO cycle. The determination of whether or not the cycle is to be

extended is made by the host after tA from the assertion of IDE_IOR[0:1]# or IDE_IOW[0:1]#.

Device never negates IDE_IORDY[0:1]. Devices keep IDE_IORDY[0:1] released, and no wait is generated.

Device negates IDE_IORDY[0:1] before tA but causes IDE_IORDY[0:1] to be asserted before tA. IDE_IORDY[0:1] is

released, and no wait is generated.

Device negates IDE_IORDY[0:1] before tA. IDE_IORDY[0:1] is released prior to negation and may be asserted for no

more than 5 ns before release. A wait is generated.

The cycle completes after IDE_IORDY[0:1] is reasserted. For cycles where a wait is generated and IDE_IOR[0:1]# is

asserted, the device places read data on IDE_DATA[15:0] for tRD before asserting IDE_IORDY[0:1].

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