ATXP032 datasheet(45/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

Figure 10-3. Write Enable in Octal Mode — DDR

10.2

Write Disable (04h)

The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status/Control register to the

logic “0” state. With the WEL bit reset, all Byte/Page Program, Erase, Program OTP Security Register, and Write

Status Register commands are not executed. Other conditions can also cause the WEL bit to be reset; for more

details, refer to the WEL bit section of the Status/Control register description.

The Write Disable command is ignored if a program or erase operation is already in progress. To halt an operation

already in progress, use the Reset command.

To issue the Write Disable command, the CS pin must first be asserted and the 04h command must be clocked

into the device. No address bytes need to be clocked into the device, and any data clocked in after the command is

ignored. When the CS pin is deasserted, the WEL bit in the Status/Control register is reset to a logic “0”. The

complete command must be clocked into the device before the CS pin is deasserted, and the CS pin must be

deasserted on a whole byte boundary (multiples of eight bits); otherwise, the device aborts the operation and the

state of the WEL bit does not change.

Figure 10-4. Write Disable

06h

Opcode

I/O7-0

SCK

MSB

Opcode

High Impedance

SCK

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