ATXP032 datasheet(61/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

protected, then the individual Sector Protection Registers can be read with the Read Sector Protection Registers

command to determine which sectors are in fact protected.

12.1.6 WEL Bit

The WEL bit indicates the current status of the internal write enable latch. When the WEL bit is in the logic “0” state,

the device does not accept any Program, Erase, Protect Sector, Unprotect Sector, or Write Status Register

commands. The WEL bit defaults to the logic “0” state after a device power-up or reset. In addition, the WEL bit is

reset to the logic “0” state automatically under the following conditions:

Write disable operation completes successfully

Write Status register operation completes successfully or aborts

Protect sector operation completes successfully or aborts

Unprotect sector operation completes successfully or aborts

Byte/Page program operation completes successfully or aborts

Block erase operation completes successfully or aborts

Chip erase operation completes successfully or aborts

If the WEL bit is in the logic “1” state, it is not reset to a logic “0” if an operation aborts due to an incomplete or

unrecognized command being clocked into the device before the CS pin is deasserted. In order for the WEL bit to

be reset when an operation aborts prematurely, the entire command for a Program, Erase, Protect Sector,

Unprotect Sector, or Write Status Register command must have been clocked into the device.

12.1.7 RDY/BSY Bit

The RDY/BSY bit is used to determine whether or not an internal operation, such as a program or erase, is in

progress. To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status/Control

“1” to a logic “0”. See also Section 12.10, Active Status Interrupt (25h).

12.2

Status/Control Register Byte 2

Status/Control register byte 2 contains the fields listed inTable 12-5. Detailed description of each bit follows below.

Note that when reading Status/Control register byte 2 while in ultra-deep power-down, all bits are read as 1.

Table 12-5. Status/Control Register – Byte 2

Bit

Acronym

Name

Type (1)

Default

Description

SDR/DDR

Select SDR or DDR mode

R/W

SDR - Single data rate mode (Default)

DDR - Dual data rate mode

AUDPD(2)

Auto Ultra-Deep Power-Down

enable

R/W

Illegal combination - Reserved for future use

AUDPD Set: Go to UDPD after Program/Erase

ADPD (2)

Auto Deep Power-Down

enable

ADPD Set: Go to DPD after Program/Erase

Normal mode - Go to Standby after Program/Erase

TERE

Terminate enabled

R/W

Terminate command is disabled (default)

Terminate command is enabled

OME

Octal mode enable

R/W

Octal mode enabled

SPI mode enabled

Reserved for future use.

R/W

Reserved. Must be written as zero.

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