ATXP032 datasheet(24/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

Address (4 bytes):

2 clock cycles (eliminated for the next consecutive line)

Dummy cycles:

14.5 clock cycles (eliminated for the next consecutive line)

Data (16 Bytes):

8 clock cycles

The behavior of the “Burst Read with Wrap (0Ch)” instruction is controlled by the W7 - W5 bits in as described in

Table 12-6, Status/Control Register Byte 3.

The wrap length and wrap mode parameters set by the W7 - W5 bits in one SPI mode is still valid in the other SPI

mode and can also be re-configured by the “Write Status Registers (71h)” instruction. See Table 12-7 for details on

wrap bit settings.

Once W7 - W5 are set, all the following “Burst Read with Wrap (0Ch)” instructions use the W7 - W5 setting to

access the 8/16/32-byte section within any page.

If W7 is cleared, the device operates in wrap-around mode. The “Burst Read with Wrap (0Ch)” instruction will read

to the end of the fixed length section (cache line), wrap around to the beginning of the section and continue reading

the same cache line continuously for as long as additional clock pulses are sent to SCK. There is no delay caused

by the wrap around, the first byte of the cache line follows immediately after the last. This operation is shown in

Figure 8-5. This mode of operation is included for compatibility with other XiP devices, and for MCUs that do not

support the continuous mode.

Figure 8-5.

Burst Read with Wrap, Wrap Around Mode (W7 = 0)

An example of this operation in wrap-around mode is shown in Figure 8-6. Here the wrap length is set to 8 for

simplicity. The requested address is 1E34h. The device therefore reads 1E34h first, followed by 1E35h, 1E36h,

and 1E37h. This is the end of the 8-byte cache line. The next address to be read out is 1E30h, followed by 1E31h,

1E32h, and 1E33h. If the read operation continues, the device outputs 1E34h again, and this loop continues for as

long as the device is clocked.

Figure 8-6.

Burst Read with Wrap Example, Wrap Around Mode (W7 = 0), Wrap Length 8, Requested Address = 1E34h

If W7 is set, the device operates in continuous mode. This is the preferred mode for maximum XiP performance for

cached MCUs. For the first cache line, the continuous mode operates the same way as the wrap-around mode.

The “Burst Read with Wrap (0Ch)” instruction reads to the end of the line, then wraps around to the beginning and

Byte 0

First Byte of

Cache Line

Last Byte of

Cache Line

Note: Each transition

shown represents one byte (8 bits)

Byte X-1

Last Byte

Read

Byte N

First Byte

Read

Byte X

Address

Requested

Note: Each transition

shown represents one byte (8 bits)

Last Byte

Read

First Byte

Read

1E30h

1E31h

1E32h

1E33h

1E34h

1E35h

1E36h

1E37h

Address

Requested

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