ATXP032 datasheet(62/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

12.2.1 SDR/DDR Bit

The SDR/DDR bit is used to determine if the device is running in SDR or DDR mode. The default mode after power

up is SDR. See Section 6.3 for details about Dual Data Rate Operation.

12.2.2 AUDPD and ADPD Bits

The AUDPD and ADPD bits are used to enable the Ultra-deep Power-down (UDPD) mode and Deep Power-down

(DPD) mode respectively. The default setting after power up is always 00, the device does not use any of these

modes unless they are specifically enabled. Only one of the AUDPD and ADPD bits can be active at any given

time, attempting to write both to 1 at the same time is an illegal combination.

See Section 13.3, Auto Deep Power-Down Mode after a Program or Erase Operation, and Section 13.6, Auto

Ultra-Deep Power-Down Mode after a Program or Erase Operation, for details about these operations.

The AUDPD bit is cleared every time the device goes into UDPD mode, so it has to be set again if another program

or erase operation followed by auto ultra-deep power-down is wanted. When using the AUDPD bit, the device

switches to Standard SPI Mode within t

AUDPD after the Program or Erase command is initiated. All Status read

operations, both while the program or erase operation is still in progress and after the device has entered UDPD,

can therefore be done using Standard SPI mode.

The ADPD bit is cleared every time the device goes into DPD. The device remains in the same communication

mode when entering and exiting from DPD.

Note: Program Suspend and Erase Suspend commands cannot be used if the ADPD or AUDPD bits are set.

12.2.3 TERE Bit

The TERE bit is used to enable or disable the Terminate Operation command. When the TERE bit is in the logic 0

state (the default state after power-up), the Terminate Operation command is disabled and any attempts to reset

the device using the Terminate command is ignored. When the TERE bit is in the logic 1 state, the Terminate

command is enabled.

The TERE bit retains its state as long as power is applied to the device. Once set to the logic 1 state, the TERE bit

remains in that state until it is modified using the Write Status Register Byte 2 (31h) command or until the device

has been power cycled. The Terminate command itself will not change the state of the TERE bit.

12.2.4 OME Bit

The OME bit is used to enable the octal mode. The default setting after power up is always 0, so the device always

wakes up in standard SPI mode. See Section 6.2 for details about Octal Mode.

Program Suspend status

No program operation has been suspended.

A sector is program suspended.

Erase Suspend status

No sectors are erase suspended.

A sector is erase suspended.

R/W = Readable and writable

R = Readable only

Do not use Program/Erase Suspend command if AUDPD or ADPD bits are set.

Table 12-5. Status/Control Register – Byte 2

Bit

Acronym

Name

Type (1)

Default

Description

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