ATXP032 datasheet(55/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

The WEL bit in the Status/Control register is reset back to the logic “0” state if the OTP Security register program

cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the CS pin being

deasserted before a whole byte is finished, or because the user attempts to write a portion of the OTP Security

Warning:

Each byte of the user programmable portion of the security register can only be programmed one time.

The behavior of the device if a user tries to overwrite an already written byte cannot be guaranteed.

While the device is programming the OTP Security register, the Status/Control register can be read and indicates

that the device is busy. For faster throughput, it is recommended that the Status/Control register be polled rather

than waiting the t

OTPP time to determine if the data bytes have finished programming. At some point before the OTP

Security register programming completes, the WEL bit in the Status/Control register is reset back to the logic “0”

state.

If the device is powered-down during the OTP Security register program cycle, then the contents of the 128-byte

user programmable portion of the OTP Security register cannot be guaranteed and cannot be programmed again.

The Program OTP Security register command utilizes the internal 256-byte buffer for processing. Therefore, the

contents of the buffer is altered from its previous state when this command is issued.

Figure 11-1. Program OTP Security Register

Figure 11-2. Program OTP Security Register in Octal Mode — SDR

SCK

10 11

37 38

42 43

40 41

High-Impedance

A A A A

A A A

A A

MSB

Opcode

Address Bits A31-A0

Data In Byte 1

Data In Byte n

Byte 0

Byte 1

Data In

A23-16

A15-8

A7-0

A31-24

Address

9Bh

Opcode

I/O7-0

SCK

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