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ATXP032

DS-ATXP032–114I–4-2020

Figure 9-15. Block Erase in Octal Mode — DDR

9.5

Chip Erase (60h or C7h)

The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip

Erase command can be started, the Write Enable command must have been previously issued to the device to set

the WEL bit of the Status/Control Register to a logic “1” state.

Two commands (60h and C7h) can be used for the Chip Erase command. There is no difference in device

functionality when utilizing the two commands, so they can be used interchangeably. To perform a Chip Erase, one

of the two commands must be clocked into the device. Since the entire memory array is to be erased, no address

bytes need to be clocked into the device, and any data clocked in after the command is ignored. When the CS pin

is deasserted, the device erases the entire memory array. The erasing of the device is internally self-timed and

should take place in a time of t

CHPE.

The complete command must be clocked into the device before the CS pin is deasserted, and the CS pin must be

deasserted on a whole byte boundary (multiples of eight bits); otherwise, no erase is performed. In addition, if any

sector in the memory array is in the protected state, then the Chip Erase command is not executed, and the device

returns to the idle state once the CS pin has been deasserted. The WEL bit in the Status/Control register is reset

back to the logic “0” state if the CS pin is deasserted before a whole byte is finished, or if the memory is in the

protected state.

While the device is executing a successful erase cycle, the Status/Control register can be read and indicates that

the device is busy. For faster throughput, it is recommended that the Status/Control register be polled rather than

waiting the t

CHPE time to determine if the device has finished erasing. At some point before the erase cycle

completes, the WEL bit in the Status/Control register is reset back to the logic “0” state.

The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase

properly. If an erase error occurs, it is indicated by the EPE bit in the Status/Control register.

Address

Bits A

-A

I/O7-0

SCK

Opcode

(20h, 52h

or D8h)

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