MMPF0100 datasheet(19/136 Pages) NXP

19 / 136 page

NXP Semiconductors

PF0100

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

VGEN5_SEQ

VGEN6_VOLT

2.8 V

3.3 V

3.0 V

2.8 V

3.3 V

2.8 V

VGEN6_SEQ

PU CONFIG,

SEQ_CLK_SPEED

1.0 ms

2.0 ms

1.0 ms

0.5 ms

2.0 ms

1.0 ms

PU CONFIG,

SWDVS_CLK

6.25 mV/

μs

1.5625 mV

μs

12.5 mV/

μs

12.5 mV/

μs

12.5 mV/

μs

12.5 mV/

μs

6.25 mV/

μs

6.25 mV/

μs 6.25 mV/μs

1.5625 mV/

μs

1.5625 mV/

μs

12.5 mV/

μs

PU CONFIG,

PWRON

Level sensitive

SW1AB CONFIG

SW1AB Single Phase, SW1C Independent Mode, 2.0 MHz

SW1ABC Single

Phase, 2.0 MHz

SW1AB Single Phase, SW1C

Independent mode, 2.0 MHz

SW1C CONFIG

2.0 MHz

SW2 CONFIG

2.0 MHz

SW3A CONFIG

SW3AB Single Phase, 2.0 MHz

SW3B CONFIG

2.0 MHz

SW4 CONFIG

No VTT, 2.0 MHz

PG EN

RESETBMCU in default mode

Notes

25.

For designs using the i.MX 6SoloLite, it is recommended to use the F3 OTP option instead of the F1 OTP option

and F4 OTP option instead of the F2 OTP option.

Table 10. Start-up configuration (continued)

Registers

Default

configuration

Pre-programmed OTP configuration

All devices

F1(25)

F2(25)

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