MMPF0100 datasheet(100/136 Pages) NXP

100 / 136 page

100

NXP Semiconductors

PF0100

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.5

Control interface I2C block description

The PF0100 contains an I2C interface port which allows access by a processor, or any I2C master, to the register set. Via these registers

the resources of the IC can be controlled. The registers also provide status information about how the IC is operating.

The SCL and SDA lines should be routed away from noisy signals and planes to minimize noise pick up. To prevent reflections in the SCL

and SDA traces from creating false pulses, the rise and fall times of the SCL and SDA signals must be greater than 20 ns. This can be

accomplished by reducing the drive strength of the I2C master via software. The i.MX6 I2C driver defaults to a 40

Ω drive strength. It is

recommended to use a drive strength of 80

Ω or higher to increase the edge times. Alternatively, this can be accomplished by using small

capacitors from SCL and SDA to ground. For example, use 5.1 pF capacitors from SCL and SDA to ground for bus pull-up resistors of

4.8 k

Ω.

6.5.1

I2C device ID

I2C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing for bus

conflict avoidance, fuse programmability is provided to allow configuration for the lower 3 address LSB(s). Refer to 6.1.2 One time

programmability (OTP), page 21 for more details. This product supports 7-bit addressing only; support is not provided for 10-bit or general

call addressing. Note, when the TBB bits for the I2C slave address are written, the next access to the chip, must then use the new slave

address; these bits take affect right away.

6.5.2

I2C operation

The I2C mode of the interface is implemented generally following the fast mode definition which supports up to 400 kbits/s operation

(exceptions to the standard are noted to be 7-bit only addressing and no support for general call addressing.) Timing diagrams, electrical

specifications, and further details can be found in the I2C specification, which is available for download at:

http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf

I2C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB and each byte

is sent out unless a STOP command or NACK is received prior to completion.

The following examples show how to write and read data to and from the IC. The host initiates and terminates all communication. The host

sends a master command packet after driving the start condition. The device responds to the host if the master command packet contains

the corresponding slave address. In the following examples, the device is shown always responding with an ACK to transmissions from

the host. If at any time a NACK is received, the host should terminate the current transaction and retry the transaction.

Figure 33. I2C write example

Figure 34. I2C read example

Device

Address

Packet

Type

START

R / W

Host SDA

Slave SDA

Master Driven Data

( byte

STOP

Host can

also drive

another

Start instead

of Stop

Device

Address

Device Address

Packet

Type

START

R/W

STOP

START

R/W

PMIC Driven Data

Host can also

drive another

Start instead of

Stop

Host SDA

Slave SDA

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