MMPF0100 datasheet(31/136 Pages) NXP

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NXP Semiconductors

PF0100

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.4.2.1

Turn on events

From off and sleep modes, the PMIC is powered on by a turn-on event. The type of turn-on event depends on the configuration of PWRON.

PWRON may be configured as an active high when PWRON_CFG = 0, or as the input of a mechanical switch when PWRON_CFG = 1.

VIN must be greater than UVDET for the PMIC to turn-on. When PWRON is configured as an active high and PWRON is high (pulled up

to VSNVS) before VIN is valid, a VIN transition from 0.0 V to a voltage greater than UVDET is also a Turn-on event. See the state diagram,

Figure 8, and the Table 26 for more details. Any regulator enabled in the sleep mode remains enabled when transitioning from sleep to

on, i.e., the regulator does not turn off and then on again to match the start-up sequence. The following is a more detailed description of

the PWRON configurations:

• If PWRON_CFG = 0, the PWRON signal is high and VIN > UVDET, the PMIC turns on; the interrupt and sense bits, PWRONI and

PWRONS respectively, is set.

• If PWRON_CFG = 1, VIN > UVDET and PWRON transitions from high to low, the PMIC turns on; the interrupt and sense bits,

PWRONI and PWRONS respectively, sets.

The sense bit shows the real time status of the PWRON pin. In this configuration, the PWRON input can be a mechanical switch

debounced through a programmable debouncer, PWRONDBNC[1:0], to avoid a response to a very short (i.e., unintentional) key press.

The interrupt is generated for both the falling and the rising edge of the PWRON pin. By default, a 30 ms interrupt debounce is applied to

both falling and rising edges. The falling edge debounce timing can be extended with PWRONDBNC[1:0] as defined in Table 27. The

interrupt is cleared by software, or when cycling through the OFF mode.

6.4.2.2

Turn off events

6.4.2.2.1

PWRON pin

The PWRON pin is used to power off the PF0100. The PWRON pin can be configured with OTP to power off the PMIC under the following

two conditions:

1. PWRON_CFG bit = 0, SWxOMODE bit = 0 and PWRON pin is low.

2. PWRON_CFG bit = 1, SWxOMODE bit = 0, PWRONRSTEN = 1 and PWRON is held low for longer than 4.0 seconds.

Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.

6.4.2.2.2

Thermal protection

If the die temperature surpasses a given threshold, the thermal protection circuit powers off the PMIC to avoid damage. A turn-on event

does not power on the PMIC while it is in thermal protection. The part remains in off mode until the die temperature decreases below a

given threshold. There are no specific interrupts related to this other than the warning interrupt. See 4.2.1 Power dissipation, page 11

section for more detailed information.

6.4.2.2.3

Undervoltage detection

When the voltage at VIN drops below the undervoltage falling threshold, UVDET, the state machine transitions to the coin cell mode.

Table 27. PWRON hardware debounce bit settings

Bits

State

Turn on

debounce (ms)

Falling edge INT

debounce (ms)

Rising edge INT

debounce (ms)

PWRONDBNC[1:0]

0.0

31.25

125

31.25

750

31.25

Notes

41.

The sense bit, PWRONS, is not debounced and follows the state of the PWRON pin.

MMPF0100 Datasheet(PDF) 31 Page - NXP Semiconductors

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