MMPF0100 datasheet(13/136 Pages) NXP

13 / 136 page

NXP Semiconductors

PF0100

GENERAL PRODUCT CHARACTERISTICS

4.3.2

Current consumption

Table 9. Current consumption summary

TMIN to TMAX (See Table 3), VIN = 3.6 V, VDDIO = 1.7 V to 3.6 V, LICELL = 1.8 V to 3.3 V, VSNVS = 3.0 V, typical external component

values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VDDIO = 3.3 V, LICELL = 3.0 V, VSNVS = 3.0 V and

25 °C, unless otherwise noted.

Mode

PF0100 conditions

System conditions

Typical

MAX

Unit

Notes

Coin Cell

VSNVS from LICELL

All other blocks off

VIN = 0.0 V

VSNVSVOLT[2:0] = 110

No load on VSNVS

4.0

7.0

μA

(17),(19),

(23)

Off

MMPF0100

VSNVS from VIN or LICELL

Wake-up from PWRON active

32 k RC on

All other blocks off

VIN

≥ UVDET

No load on VSNVS, PMIC able to wake-up

μA

(18),(19)

Off

MMPF0100A

VSNVS from VIN or LICELL

Wake-up from PWRON active

32 k RC on

All other blocks off

VIN

≥ UVDET

No load on VSNVS, PMIC able to wake-up

μA

(18),(19)

Sleep

VSNVS from VIN

Wake-up from PWRON active

Trimmed reference active

SW3A/B PFM

Trimmed 16 MHz RC off

32 k RC on

VREFDDR disabled

No load on VSNVS. DDR memories in self

refresh

122

220(22)

250(21)

μA

(19)

Standby

MMPF0100

VSNVS from either VIN or LICELL

SW1A/B combined in PFM

SW1C in PFM

SW2 in PFM

SW3A/B combined in PFM

SW4 in PFM

SWBST off

Trimmed 16 MHz RC enabled

Trimmed reference active

VGEN1-6 enabled

VREFDDR enabled

No load on VSNVS. Processor enabled in

low power mode. All rails powered on

except boost (load = 0 mA)

297

450 (20)

1000 (22)

μA

(19)

Standby

MMPF0100A

VSNVS from either VIN or LICELL

SW1A/B combined in PFM

SW1C in PFM

SW2 in PFM

SW3A/B combined in PFM

SW4 in PFM

SWBST off

Trimmed 16 MHz RC enabled

Trimmed reference active

VGEN1-6 enabled

VREFDDR enabled

No load on VSNVS. Processor enabled in

low power mode. All rails powered on

except boost (load = 0 mA)

297

450 (22)

550(21)

μA

(19)

Notes

17.

Refer to Figure 4 for coin cell mode characteristics over temperature.

18.

When VIN is below the UVDET threshold, in the range of 1.8 V

≤ VIN < 2.65 V, the quiescent current increases by 50 μA, typically.

19.

For PFM operation, headroom should be 300 mV or greater.

20.

From 0 °C to 85 °C

21.

From -40 °C to 105 °C, applicable only to extended industrial parts.

22.

From -40 °C to 85 °C, applicable to consumer, industrial and extended industrial part numbers.

23.

Additional current may be drawn in the coin cell mode when RESETBMCU is pulled up to VSNVS due an internal path from RESETBMCU to VIN.

The additional current is < 30

μA with a pull up resistor of 100 kΩ. The i.MX 6x processors have an internal pull up from the POR_B pin to the

VDD_SNVS_IN pin. For i.MX 6x applications, if additional current in the coin cell mode is not desired, use an external switch to disconnect the

RESETBMCU path when VIN is removed. For non-i.MX 6 applications, pull-up RESETBMCU to a rail off in the coin cell mode.

MMPF0100 Datasheet(PDF) 13 Page - NXP Semiconductors

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