MMPF0100 datasheet(36/136 Pages) NXP

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NXP Semiconductors

PF0100

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

The regulators have a strong sourcing capability and sinking capability in PWM mode, therefore the fastest rising and falling slopes are

determined by the regulator in PWM mode. However, if the regulators are programmed in PFM or APS mode during a DVS transition, the

falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS transitions in

PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation.

The following diagram shows the general behavior for the regulators when initiated with I2C programming, or standby control. During the

DVS period the overcurrent condition on the regulator should be masked.

Figure 10. Voltage stepping with DVS

6.4.4.2.2

Regulator phase clock

The SWxPHASE[1:0] bits select the phase of the regulator clock as shown in Table 36. By default, each regulator is initialized at 90 ° out

of phase with respect to each other. For example, SW1x is set to 0 °, SW2 is set to 90 °, SW3A/B is set to 180 °, and SW4 is set to 270 °

by default at power up.

The SWxFREQ[1:0] register is used to set the desired switching frequency for each one of the buck regulators. Table 38 shows the

selectable options for SWxFREQ[1:0]. For each frequency, all phases are available, allowing regulators operating at different frequencies

to have different relative switching phases. However, not all combinations are practical. For example, 2.0 MHz, 90 ° and 4.0 MHz, 180 °

are the same in terms of phasing. Table 37 shows the optimum phasing when using more than one switching frequency.

Table 35. DVS speed selection for SW2, SW3A/B, and SW4

SWxDVSSPEED[1:0]

Function

SWx[6] = 0 or SWxSTBY[6] = 0

Function

SWx[6] = 1 or SWxSTBY[6] = 1

25 mV step each 2.0

μs

50 mV step each 4.0

μs

01 (default)

25 mV step each 4.0

μs

50 mV step each 8.0

μs

25 mV step each 8.0

μs

50 mV step each 16

μs

25 mV step each 16

μs

50 mV step each 32

μs

Table 36. Regulator phase clock selection

SWxPHASE[1:0]

Phase of clock sent to regulator (degrees)

180

270

Actual

Output Voltage

Example

Actual Output

Voltage

Possible

Output Voltage

Window

Internally

Controlled Steps

Output Voltage

with light Load

Initial

Set Point

Voltage

Change

Request

Internally

Controlled Steps

Output

Voltage

Requested

Set Point

Initiated by I2C Programming, Standby Control

Request for

Higher Voltage

Request for

Lower Voltage

MMPF0100 Datasheet(PDF) 36 Page - NXP Semiconductors

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