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MMPF0100 Datasheet(PDF) 135 Page - NXP Semiconductors |
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MMPF0100 Datasheet(HTML) 135 Page - NXP Semiconductors |
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135 / 136 page ![]() NXP Semiconductors 135 PF0100 REVISION HISTORY 12.0 9/2015 • Updated Table 53 • Updated Table 62 • Updated Table 77 • Updated Table 86 • Fixed typo in Table 138 • Updated Table 139 • Added Table 140 • Corrected the default register value for SW1ABMODE in Table 46 • Corrected the default register value for SW1CMODE in Table 51 • Corrected the default register value for SW2MODE in Table 60 • Corrected the default register value for SW3AMODE in Table 70 • Corrected the default register value for SW3BMODE in Table 75 • Corrected the default register value for SW4MODE in Table 84 • Updated Figure 35 13.0 12/2015 • Removed MMPF0100NPEP, MMPF0100F0EP, MMPF0100F1EP, and MMPF0100F2EP from Orderable Part Variations. No longer manufactured. • Updated Table 10 • Reformatted to newer template form and style 14.0 3/2016 • Updated SW2 current capability from 2000 mA to 2500 mA for F9/FA versions 15.0 5/2016 • Changed Table 10 row - Default I2C Address from 0x80 to 0x08 for F9 and FA 16.0 9/2016 • Added NP version to OTP's with SW2 current capability of 2500 mA • Added MMPF0100FBANES part number to Table 1 • Added FB OTP option to Table 10 17.0 1/2017 • Added MMPF0100FCAEP, MMPF0100FDAEP, and MMPF0100FCANES part numbers to Table 1 • Added OTP configurations for FC and FD to Table 10 18.0 7/2019 • Updated 98ASA00405D drawing as per PCN 201906034F01 • Changed document status from Advance Information to Technical Data Revision Date Description of changes |
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