W5300 datasheet(48/128 Pages) WIZNET

48 / 128 page

4.1 Mode Register

MR (Mode Register) [R/W] [0x08000/----][0x3800 or 0xB800]

MR sets the mode of W5300 such like that host Interface mode, MSB/LSB swap of

Sn_TX_FIOR & Sn_RX_FIFOR, S/W reset, internal TX/RX memory test, MSB/LSB swap of

data bus and address mode.

MR0

0x08000

DBW

MPF

WDF2

WDF1

WDF0

RDH

----

U(R)

0(R)

MR1

0x08001

RST

PPPoE

DBS

IND

----

MR(15:8)/MR0(7:0)

Bit

Symbol

Description

DBW

Data Bus Width

0 : 8 bit data bus

1 : 16 bit data bus

At the reset time of W5300, it is fixed according to logic level of PIN

“BIT16EN”. After reset, it is not changed.

Refer to BIT16EN description of “1.1 PIN Layout”

MPF

MAC Layer Pause Frame

0 : Normal frame

1 : Pause frame

It is set as ‘1’, when pause frame is received from router or switch. When set

as ‘1’, all data transmit is paused until changing to ‘0’.

WDF2

Write Data Fetch Time

When Host-Write operation

, since ‘/CS’ is asserted low, W5300 fetches

Write-Data after WRF X PLL_CLK.

If Host-Write o

peration is finished (‘/CS’ is de-asserted high) before WRF X

PLL_CLK, Write-

Data is fetched at the time that ‘/CS’ is de-asserted high.

WDF1

WDF0

RDH

Read Data Hold Time

W5300 Datasheet(PDF) 48 Page - WIZnet Co., Ltd

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