W5300 datasheet(49/128 Pages) WIZNET

49 / 128 page

0 : No use data hold time

1 : Use data hold time (2 X PLL_CLK)

When Host-Read operation, W5300 holds the Read-Data during 2 X

PLL_CLK after Host-Read

operation is finished (‘/CS’ is de-asserted high). In

this case, be careful of collision of data bus.

Reserved

FIFO Swap Bit

0 : Disable swap

1 : Enable swap

It swaps the most significant byte (MSB) and least significant byte (LSB).

Basically, the byte ordering of W5300 is big-endian. If the target host system

based

little-endian,

you

can

switch

the

byte

ordering

Sn_TX

_FIFOR/Sn_RX_FIFOR by setting this bit as ‘1’, and use it as like

little-endian.

MR(7:0)/MR1(7:0)

Bit

Symbol

Description

RST

S/W Reset

If it’s set as ‘1’, W5300 is reset.

This bit is automatically cleared after reset.

Reserved

Memory Test Bit

0 : Disable internal TX/RX memory test

1 : Enable internal TX/RX memory test

Basically, internal TX memory of W5300 supports Host-Write operation

through Sn_TX_FIFOR, and internal RX memory does Host-Read operation

through Sn_RX_FIFOR. However if this b

it is set as ‘1’, internal TX/RX

memory supports both of Host-Read and Host-Write operation through

Sn_TX_FIFOR/Sn_RX_FIFOR , and verifies the internal TX/RX memory.

After testing W5300 internal TX/RX memory, be sure to reset or close the

SOCKET.

For the detail, refer to

“How to test internal TX/RX memory”.

Ping Block Mode

W5300 Datasheet(PDF) 49 Page - WIZnet Co., Ltd

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