W5300 datasheet(26/128 Pages) WIZNET

26 / 128 page

3. W5300 Registers

W5300 register is composed of MR(to decide direct or indirect address mode), IDM_AR &

IDM_DR(only used at the indirect address mode) and COMMON registers and SOCKET

registers.

MR, IDM_AR, and IDM_DR register are mapped in T.M.S. COMMON & SOCKET registers are

mapped in T.M.S or W.M.S (W5300 internal Memory Space) according to address mode.

All W5300 registers are 1Byte, 2Bytes, 4Bytes or 6Bytes. According to data bus width of target

host system, the access is processed

– 2bytes address offset at the 16bit data bus and 1 byte

address offset at the 8bit data bus.

When mapping W5300 registers in T.M.S, the physical T.M.S address of W5300 register is

calculated as below.

The byte ordering of W5300 registers is big-endian

– low address byte is used as the most

significant byte.

[Register Notation]

MR : MR register

MR0 : Low address register of MR (Address offset - 0x000 ), Most significant byte

MR1 : High address register of MR (Address offset

– 0x001), Least significant byte

MR(15:5) : 11 bit (from 15th bit to 5th bit of MR register)

MR(0) : 0th bit of MR register, 0th bit of MR1

MR(13) : 13th bit of MR register, 5th bit of MR0

MR0(7) : 15th bit of MR register, Most significant bit of MR0

MR(DWB) : MR의 DWB bit

(DWB : Bit Symbol)

SHAR : Source Hardware Address Register

SHAR0 : 1ST address register of SHAR (Address offset

– 0x008)

SHAR1 : 2nd address register of SHAR (Address offset

– 0x009)

SHAR2 : 3rd address register of SHAR (Address offset

– 0x00A)

SHAR3 : 4th address register of SHAR (Address offset

– 0x00B)

SHAR4 : 5th Address register of SHAR (Address offset

– 0x00C)

SHAR5 : 6th address register of SHAR (Address offset

– 0x00D)

Physical Address of W5300 Reg

= Base Address of T.M.S + Address offset of W5300 Reg

W5300 Datasheet(PDF) 26 Page - WIZnet Co., Ltd