W5300 datasheet(15/128 Pages) WIZNET

15 / 128 page

1.3 Host Interface Signals

Symbol

Type

Description

/RESET

RESET

Hardware Reset Signal.

It initializes W5300. RESET should be held at least 2us after low assert,

and wait for at least 10ms after high de-assert in order for PLL logic to

be stable.

Refer to RESET t

iming of “7 Electrical Specification”

W5300 does not support Power-On-Reset. Therefore, it should be

manually designed in the target system.

BIT16EN

16/8 BIT DATA BUS SELECT

High : 16 bit data bus

Low : 8 bit data bus

It determinates data bus width of W5300.

At reset time, it is latched in 15th

Bit(‘BW’)of Mode register(MR).

After reset, its change is ignored. It means data bus wi

dth can’t be

changed after reset. When using 8 bit data bus, it should be connected

to ground.

ADDR9-0

ADDRESS

System address bus.

These are selected by host interface mode and data bus width of

W5300. When using 16 bit data bus, ADDR0 is internally ignored.

Refer to “6.External Interface”.

DATA[15:8]

DATA

System high data bus.

These are used for read/write operation of W5300 register.

In case of using 8 bit data bus, These are driven as High-Z.

DATA[7:0]

IO8

DATA

System low data bus.

These are used for read/write operation of W5300 register.

/CS

CHIP SELECT

Chip select signal.

W5300 Datasheet(PDF) 15 Page - WIZnet Co., Ltd

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