W5300 datasheet(52/128 Pages) WIZNET

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Ex2) When the host reads IR(0x0FE)

and saves it in variable ‘val’,

16 Bit Data Bus Width ( MR(DBW) = ‘1’)

8 Bit Data Bus Width ( MR(DBW) = ‘0’)

IDM_AR = 0x0002

val = IDM_DR

IDM_AR0 = 0x00

IDM_AR1 = 0x02

val = IDM_DR0

val = (val << 8) + IDM_DR1

IDM_AR(0x08002/----)

IDM_AR0(0x08002/----)

IDM_AR1(0x08003/----)

0x00

0x02

IDM_DR(0x08004/----)

IDM_DR0(0x08004/----)

IDM_DR1(0x08005/----)

MSB(IR0) of IR

LSB(IR1) of IR

4.3 COMMON Registers

IR (Interrupt Register) [R/W] [0x08002/0x002] [0x0000]

IR is the register to notify W5300 interrupt type to the host. When any interrupt occurs, the

related bit of IR is set as ‘1’, and if the related interrupt mask bit is ‘1’ then ‘/INT’ signal is

asserted low.

‘/INT’ signal keeps low until all bits of IR becomes ‘0’. If all bits of IR become ‘0’, it is de-asserted

high. In order to clear IR0’s bit which was set as ‘1’, the host should write the bit as ‘1’. In case

of IR1’s bit which was set as ‘1’, it is automatically cleared when clearing all bits of the related

Sn_IR.

IR0

0x08002

IPCF

DPUR

PPPT

FMTU

0x002

IR1

0x08003

S7_INT

S6_INT

S5_INT

S4_INT

S3_INT

S2_INT

S1_INT

S0_INT

0x003

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