W5300 datasheet(87/128 Pages) WIZNET

87 / 128 page

Sn_TX_FIFOR. If MR(MT) = '0', only the Host-Write of internal TX memory is allowed through

Sn_TX_FIFOR. But if MR(MT) is '1', both of Host-Read and Host-Write are allowed. Be sure to

set it as '0' after verifying interface between W5300 and the host system. (for the detail, refer to

“How to Test Internal TX/RX memory”)

If the host system uses 8 bit data bus width, Sn_TX_FIFOR0 and Sn_TX_FIFOR1 should be

accessed in a pair. When copying 1 byte data into internal TX memory, the host writes the 1

byte data in Sn_TX_FIFOR0 and dummy data in Sn_TX_FIFOR1.

Sn_TX_FIFOR should be accessed with 2 byte size. Access the Sn_TX_FIFOR0 of low address

it is not allowed to access other W5300 registers except for Sn_TX_FIFOR1.

When any data is written by the host through Sn_TX_FIFOR, the data is sequentially copied into

internal TX memory. The data of Sn_TX_FIFOR0 and Sn_TX_FIFOR1 are respectively saved in

low and high addresses of internal TX memory. The data in internal TX memory is transmitted in

order of low address by SEND or SEND_MAC command.

Ex1) Sn_TX_FIFOR = 0x1122

Sn_TX_FIFOR(0x0822E+0x40n/0x22E+0x040n)

Sn_TX_FIFOR0(0x0822E+0x40n/0x22E+0x040n)

Sn_TX_FIFOR1(0x0822F+0x40n/0x22F+0x040n)

0x11

0x22

Ex2) When transmitting

5 Byte String Data “abcde” (abcde - 0x61 0x62 0x63 0x64 0x65)

16 Bit Data Bus Width ( MR(DBW) = ‘1’)

8 Bit Data Bus Width ( MR(DBW) = ‘0’)

Sn_TX_FIFOR = 0x6162

Sn_TX_FIFOR = 0x6364

Sn_TX_FIFOR = 0x6500

Sn_TX_WRSR0 = 0x0000

Sn_TX_WRSR1 = 0x0005

Sn_CR = 0x0020 (SEND command)

Sn_TX_FIFOR0 = 0x61

Sn_TX_FIFOR1 = 0x62

Sn_TX_FIFOR0 = 0x63

Sn_TX_FIFOR1 = 0x64

Sn_TX_FIFOR0 = 0x65

Sn_TX_FIFOR1 = 0x00

Sn_TX_WRSR0 = 0x00

Sn_TX_WRSR1 = 0x00

Sn_TX_WRSR2 = 0x00

Sn_TX_WRSR2 = 0x05

Sn_CR1 = 0x20 (SEND command)

W5300 Datasheet(PDF) 87 Page - WIZnet Co., Ltd