W5300 datasheet(19/128 Pages) WIZNET

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MII_RXD3

Receive Data Input

When MII_RXDV is high, the received packet is synchronized

with MII_RXC and inputs in nibble unit.

MII_RXD3 is MSB.

MII_RXD2

MII_RXD1

MII_RXD0

MII_RXDV

Receive Data Valid

This signal indicates the presence of received packet from

MII_RXD[3:0].

It is asserted high when the first nibble data of the received

packet is valid on MII_RXD[3:0] and is de-asserted low after

the last nibble

data of receive

packet clocked in

MII_RXD[3:0].

It is valid when MII_RXC is at rising edge.

MII_RXC

Receive Clock Input

It is continuous receive clock from the external PHY. It is

25MHz at the 100Base TX and 2.5MHz at the 10BaseT.

Receive clock is used for timing reference of MII_RXD[3:0] and

MII_RXDV.

Rising Edge Sensitive.

/FDX

IDL

Full-Duplex Select

0 : Full-duplex

1 : Half-duplex

It is input signal from PHY that indicates link status of external

PHY. Most of PHYs support auto-negotiation and notifies the

result to network indicator LED or other signals. It can be

connected to those signals and also it can be configurable

manually by connecting high or low.

Recommend for the better performance.

MII interface signal line length should not be more than 25cm if possible.

The length of MII_TXD[3:0] should be same if possible.

The length of MII_RXD[3:0] should be same if possible.

The length of MII_TXC should not be longer than MII_TXD[3:0] signal line by 2.5cm.

The length of MII_RXC should not be longer than MII_RXD[3:0] signal line by 2.5cm.

W5300 Datasheet(PDF) 19 Page - WIZnet Co., Ltd

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